Memory management device

ABSTRACT

A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of PCT Application No.PCT/JP2010/053817, filed Mar. 8, 2010 and based upon and claiming thebenefit of priority from prior Japanese Patent Applications No.2009-169371, filed Jul. 17, 2009; No. 2010-048328, filed Mar. 4, 2010;No. 2010-048329, filed Mar. 4, 2010; No. 2010-048331, filed Mar. 4,2010; No. 2010-048332, filed Mar. 4, 2010; No. 2010-048333, filed Mar.4, 2010; No. 2010-048334, filed Mar. 4, 2010; No. 2010-048335, filedMar. 4, 2010; No. 2010-048337, filed Mar. 4, 2010; No. 2010-048338,filed Mar. 4, 2010; and No. 2010-048339, filed Mar. 4, 2010, the entirecontents of all of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory management device that managesaccess to a memory.

2. Description of the Related Art

In a conventional information processing device, a volatilesemiconductor memory, for example, a DRAM (Dynamic Random Access Memory)is used as a main memory device of a processor. Further, in aconventional information processing device, a nonvolatile semiconductormemory is used as a secondary storage device in combination with thevolatile semiconductor memory.

Jpn. Pat. Appln. KOKAI Publication No. 2008-242944 (Patent Literature 1)proposes an integrated memory management device. In the integratedmemory management device, a NAND flash memory is used as a main memoryfor an MPU. Further, in Patent Literature 1, a primary cache memory ofthe MPU, a secondary cache memory, and the NAND flash memory, which isthe main memory, are handled in the same memory layer. A cachecontroller of the integrated memory management device implements, inaddition to memory management of the primary cache memory and thesecondary cache memory, memory management of the main memory.

Jpn. Pat. Appln. KOKAI Publication No. 7-146820 (Patent Literature 2)discloses a technology that adopts a flash memory as the main memorydevice of an information processing device. According to PatentLiterature 2, a flash memory is connected to a memory bus of a systemvia a cache memory, which is a volatile memory. The cache memory isprovided with an address array that records information such asaddresses and an access history of data stored in the cache memory. Acontroller references an access destination address to supply data inthe cache memory or the flash memory to the memory bus or to store datain the memory bus.

Jpn. Pat. Appln. KOKAI Publication No. 2001-266580 (Patent Literature 3)discloses an invention allowing different kinds of semiconductor memorydevices to connect to a common bus.

A semiconductor memory device according to Patent Literature 3 includesa random access memory chip and a package including the random accessmemory chip. The package has a plurality of pins to electrically connectthe random access memory chip to an external device. The plurality ofpins provides a memory function commonly to the random access memorychip and a nonvolatile semiconductor memory that can electrically beerased and programmed. Each of the plurality of pins is arranged in theposition of a corresponding pin of the nonvolatile semiconductor memory.

BRIEF SUMMARY OF THE INVENTION Technical Problem

The present invention provides a memory management device capable ofefficiently using a nonvolatile semiconductor memory.

Solution to Problem

A memory management device according to an embodiment of the presentinvention controls writing into and reading from a main memory includinga nonvolatile semiconductor memory and a volatile semiconductor memoryin response to a writing request and a reading request from a processor.The memory management device includes a coloring information storageunit that stores coloring information generated based on a datacharacteristic of write target data to be written into at least one ofthe nonvolatile semiconductor memory and the volatile semiconductormemory, and a writing management unit that references the coloringinformation to determine a region into which the write target data iswritten from the nonvolatile semiconductor memory and the volatilesemiconductor memory.

Advantageous Effects of Invention

According to the present invention, a memory management device capableof efficiently using a nonvolatile semiconductor memory can be provided.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram showing an example of a structure of a memorymanagement device and an information processing device according to afirst embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a structure of thememory management device and the information processing device accordingto the first embodiment.

FIG. 3 is a diagram showing an example of a memory map of a mixed mainmemory according to the first embodiment.

FIG. 4 is a diagram showing an example of address conversion informationaccording to the first embodiment.

FIG. 5 is a diagram showing an example of a coloring table according tothe first embodiment.

FIG. 6 is a diagram illustrating an example of static color informationaccording to the first embodiment.

FIG. 7 is a flow chart showing an example of data arrangement processingaccording to the first embodiment.

FIG. 8 is a diagram showing an example of a configuration of thecoloring table according to the first embodiment.

FIG. 9 is a diagram showing a first example of a setting of static colorinformation to various kinds of data.

FIG. 10 is a diagram showing a second example of settings of staticcolor information to various kinds of data.

FIG. 11 is a flow chart showing an example of generation processing ofthe coloring table according to the first embodiment.

FIG. 12 is a flow chart showing an example of generation processing ofan entry of the coloring table according to the first embodiment.

FIG. 13 is a diagram showing a first example of an alignment of entriesof the coloring table according to the first embodiment.

FIG. 14 is a diagram showing a second example of the alignment ofentries of the coloring table according to the first embodiment.

FIG. 15 is a diagram showing an example of a method of calculating adynamic writing frequency DW_color and a dynamic reading frequencyDR_color based DR_color dynamic color information and static colorinformation.

FIG. 16 is a flow chart showing an example of reading processing of dataaccording to the first embodiment.

FIG. 17 is a flow chart showing an example of decision processing ofreading method of data according to the first embodiment.

FIG. 18 is a flow chart showing an example of writing processing of dataaccording to the first embodiment.

FIG. 19 is a flow chart showing an example of decision processing ofwriting destination region of data according to the first embodiment.

FIG. 20 is a diagram illustrating decision processing of a block intowhich data is to be written according to the first embodiment.

FIG. 21 is a graph showing an example of a change of an erasure count inan arbitrary block region of the nonvolatile semiconductor memory.

FIG. 22 shows graphs showing an example of a change when a threshold fora difference of an erasure count is set small for wear leveling.

FIG. 23 is a graph showing an example of grouping of a block region inaccordance with the erasure count.

FIG. 24 is a diagram showing determination criteria for grouping theblock region in accordance with the erasure count.

FIG. 25 is a diagram showing an example of a search of the block regionfor wear leveling.

FIG. 26 is a block diagram showing an example of a memory managementdevice further including a cache memory in the memory management device.

FIG. 27 is a block diagram showing implementation examples of the memorymanagement device, the mixed main memory, and a processor.

FIG. 28 is a block diagram showing of an example of another structureaspect of the memory management device and the information processingdevice according to the first embodiment of the present invention.

FIG. 29 is a perspective view showing an example of the plurality ofmemory management devices managing the plurality of nonvolatilesemiconductor memories.

FIG. 30 shows a physical address space of a volatile semiconductormemory according to a second embodiment.

FIG. 31 shows an example of a relationship between the coloringinformation and areas of the volatile semiconductor memory.

FIG. 32 shows another example of the relationship between the coloringinformation and the areas of the volatile semiconductor memory.

FIG. 33 shows an example of a data structure for managing a free spaceand a used space of the volatile semiconductor memory according to thesecond embodiment.

FIG. 34 shows an example of write processing to the volatilesemiconductor memory according to the second embodiment.

FIG. 35 shows an example of an erasure processing to the volatilesemiconductor memory according to the second embodiment.

FIG. 36 is diagram showing a truth value of a valid/invalid flag ofnonvolatile semiconductor memory in the address conversion informationaccording to the third embodiment of the present invention.

FIG. 37 is diagram showing a state transition of the valid/invalid flagof the nonvolatile semiconductor memory.

FIG. 38 is a flow diagram showing processing when a release of the mixedmain memory is requested, according to the third embodiment.

FIG. 39 is a diagram illustrating a formation of explicit free space inthe volatile semiconductor memory when the release of a memory in FIG.38 is requested.

FIG. 40 is a flow diagram showing processing when acquisition of themixed main memory is requested, according to the third embodiment.

FIG. 41 is a flow chart diagram showing processing when memory datareading is requested in FIG. 40.

FIG. 42 is a flow chart showing processing when memory data writing isrequested in FIG. 40.

FIG. 43 is a block diagram showing an example of a principal portion ofa functional configuration of a memory management device according to afourth embodiment of the present invention.

FIG. 44 is a diagram showing an example of a data structure of a blocksize when write target data is not classified based on the coloringinformation.

FIG. 45 is a diagram showing an example of a data structure of a blocksize when write target data is classified based on the coloringinformation.

FIG. 46 is a diagram showing an example of a relationship between theaddress conversion information the physical address space (NAND logicaladdress) of the nonvolatile semiconductor memory according to the fourthembodiment.

FIG. 47 is a diagram showing an example of a logical/physical conversiontable (NAND logical/physical conversion table) of the nonvolatilesemiconductor memory.

FIG. 48 is a data structure diagram showing an example of a reservationlist.

FIG. 49 is a flow chart showing an example of processing of a groupvalue calculation unit and a reservation list management unit accordingto the fourth embodiment.

FIG. 50 is a diagram showing an example of a state transition of theaddress conversion information according to the fourth embodiment.

FIG. 51 is a diagram showing an example of a dirty bit field accordingto a fifth embodiment.

FIG. 52 is a flow chart showing shut down processing according to thefifth embodiment.

FIG. 53 is a diagram showing the coloring table applied in the fifthembodiment.

FIG. 54 is a flow chart showing setting processing of pre-reading hintinformation according to the fifth embodiment.

FIG. 55 is a flow chart showing an example of processing of an operatingsystem when activation according to the fifth embodiment.

FIG. 56 is a block diagram showing an example of a relationship betweena virtual address region in a virtual address space and attributeinformation according to a sixth embodiment.

FIG. 57 is a flow chart showing an example of setting processing ofsecond attribute information of virtual address region data by theoperating system.

FIG. 58 is a diagram showing an example of a setting of static colorinformation based on the virtual address region data.

FIG. 59 is a diagram showing an example of a dependence relationshipbetween commands and libraries.

FIG. 60 is a diagram showing an example of scores of the commands andscores of the libraries.

FIG. 61 is a diagram showing another calculation example of the scoresof the libraries based on the scores of commands.

FIG. 62 is a diagram showing an example of a setting of static colorinformation using the scores of the libraries.

FIG. 63 is a diagram showing an example of variables or functionsbrought together by a compiler.

FIG. 64 is a diagram showing an example of a setting of the static colorinformation using the compiler.

FIG. 65 is a diagram showing an example of a setting of the static colorinformation based on a usage frequency of a dynamically generated memoryregion.

FIG. 66 is a block diagram showing an example of configurations of amemory management device, information processing device, and memorydevice according to a seventh embodiment of the present invention.

FIG. 67 is a graph showing an example of a change of an erasure count ofa memory unit.

FIG. 68 is a graph showing an example of a usage state of the memorydevice based on the erasure count of the memory device.

FIG. 69 is a graph showing an example of the usage state of the memorydevice based on a reading occurrence count of the memory device.

FIG. 70 is a flow chart showing an example of processing notifying thememory device of the usage state based on the erasure count of thememory device.

FIG. 71 is a flow chart showing an example of notifying the memorydevice of the usage state based on the reading occurrence count of thememory device H32 a.

FIG. 72 is a diagram showing an example of data included in managementinformation.

FIG. 73 is a flow chart showing an example of processing after thememory device is electrically connected to the memory management deviceuntil access to the memory device is started.

FIG. 74 is a flow chart showing processing after the memory managementdevice receives a removal notification from the memory device until thememory device becomes removable.

FIG. 75 is a diagram showing an example of removing state of the memorydevice.

FIG. 76 is a block diagram showing an example of a reuse of the memorydevice.

FIG. 77 is a block diagram showing an example of a change of an accesscount when a control executes so that an access count for one memorydevice becomes larger than an access count for another memory device,based on the coloring information.

FIG. 78 is a diagram showing an example of a configuration of a memorymanagement device according to an eighth embodiment of the presentinvention.

FIG. 79 is a schematic diagram showing a first example of dynamicswitching of nonvolatile semiconductor memories according to the eighthembodiment.

FIG. 80 is a schematic diagram showing a second example of dynamicswitching of nonvolatile semiconductor memories according to the eighthembodiment.

FIG. 81 is a state transition diagram showing a first example ofswitching control of a memory region by a switching control unitaccording to the eighth embodiment.

FIG. 82 is a state transition diagram showing a second example ofswitching control of a memory region by a switching control unitaccording to the eighth embodiment.

FIG. 83 is a block diagram showing an example of a relationship betweena memory management device according to a ninth embodiment of thepresent invention and a address space.

FIG. 84 is a flow chart showing an example of a writing operation by aprocessor 3 b and the memory management device according to the ninthembodiment.

FIG. 85 is a diagram showing an example of a configuration of aninformation processing device and a network system according to a tenthembodiment of the present invention.

FIG. 86 is a flow chart showing an example of processing of a profileinformation management unit according to the tenth embodiment.

FIG. 87 is a flow chart showing an example of upload processing ofprofile information by a user terminal according to the tenthembodiment.

FIG. 88 is a flow chart showing an example of download processing of theprofile information by the user terminal according to the tenthembodiment.

FIG. 89 is a block diagram showing an example of a network systemaccording to an eleventh embodiment of the present invention.

FIG. 90 is a block diagram showing an example of a configuration of amemory management device according to the eleventh embodiment.

FIG. 91 is a block diagram showing a first relationship between aprocessor logical address and a network logical address according to theeleventh embodiment.

FIG. 92 is a block diagram showing a second relationship between aprocessor logical address and a network logical address according to theeleventh embodiment.

FIG. 93 is a block diagram showing a third relationship between aprocessor logical address and a network logical address according to theeleventh embodiment.

FIG. 94 is a block diagram showing a fourth relationship between aprocessor logical address and a network logical address according to theeleventh embodiment.

FIG. 95 is a block diagram showing a fifth relationship between aprocessor logical address and a network logical address according to theeleventh embodiment.

FIG. 96 is a block diagram showing an example of a virtual address spaceof the network system according to the eleventh embodiment.

FIG. 97 is a block diagram showing a first example of a configuration ofthe processor logical address and the network logical address accordingto the eleventh embodiment.

FIG. 98 is a block diagram showing a second example of a configurationof the processor logical address and the network logical addressaccording to the eleventh embodiment.

FIG. 99 is a block diagram showing a third example of a configuration ofthe processor logical address and the network logical address accordingto the eleventh embodiment.

FIG. 100 is a diagram showing an example of calculation to estimate thenumber of bits of an address needed to access data stored in a largenumber of devices connected to a network.

DETAILED DESCRIPTION OF THE INVENTION

Each embodiment of the present invention will be described below withreference to drawings. In the description that follows, the samereference numerals are attached to substantially or essentially the samefunctions and elements and a description thereof is provided ifnecessary.

First Embodiment

A memory management device 1 and an information processing device 100according to a first embodiment of the present invention will bedescribed. FIG. 1 is a block diagram showing an example of the memorymanagement device and the information processing device according to thepresent embodiment.

The information processing device 100 includes the memory managementdevice 1, a mixed main memory 2, and processors 3 a, 3 b, 3 c.

The processor 3 a, 3 b, or 3 c is, for example, a MPU (Micro ProcessorUnit) or GPU (Graphical Processor Unit). The processors 3 a, 3 b, 3 cinclude primary cache memories 4 a, 4 b, 4 c and secondary cachememories 5 a, 5 b, 5 c respectively. The processors 3 a, 3 b, 3 cexecute processes 6 a, 6 b, 6 c to process various kinds of datarespectively. In the execution of the processes 6 a, 6 b, 6 c, theprocessors 3 a, 3 b, 3 c specify data by using a virtual address.

To write data (write target data) into the mixed main memory 2, theprocessors 3 a, 3 b, 3 c generate a writing request. To read data (readtarget data) from the mixed main memory 2, the processors 3 a, 3 b, 3 cgenerate a reading request.

Each of the processors 3 a, 3 b, 3 c includes a page table (not shown)for converting a virtual address into a physical address (logicaladdress for the mixed main memory 2) of the MPU or GPU. To write datainto the primary cache memories 4 a, 4 b, 4 c, the secondary cachememories 5 a, 5 b, 5 c, or the mixed main memory 2, the processors 3 a,3 b, 3 c convert a virtual address into a logical address based on thepage table to specify write target data by the logical address.Similarly, to read data from the primary cache memories 4 a, 4 b, 4 c,the secondary cache memories 5 a, 5 b, 5 c, or the mixed main memory 2,the processors 3 a, 3 b, 3 c convert a virtual address into a logicaladdress based on the page table to specify read target data by thelogical address.

Incidentally, writing into and reading from the primary cache memories 4a, 4 b, 4 c, the secondary cache memories 5 a, 5 b, 5 c, or the mixedmain memory 2 will genetically be expressed as “access” below.

The memory management device 1 manages access (writing, reading) to themixed main memory 2 by the processors 3 a, 3 b, 3 c. The memorymanagement device 1 includes a processing unit 15, a working memory 16,and an information storage unit 17. The memory management device 1stores memory usage information 11, memory specific information 12,address conversion information 13, and a coloring table 14 describedlater in the information storage unit 17. The coloring table 14 storedin the information storage unit 17 of the memory management device 1 maybe a portion of the coloring table 14 stored in nonvolatilesemiconductor memories 9, 10. For example, data of the coloring table 14used frequently of the coloring table 14 stored in the nonvolatilesemiconductor memories 9, 10 may be stored in the information storageunit 17 of the memory management device 1. The memory management device1 references the coloring table 14 and the like to manage access to themixed main memory 2 by the processors 3 a, 3 b, 3 c. Details thereofwill be described later.

The mixed main memory 2 includes a first memory, a second memory, and athird memory. The first memory has a greater accessible upper limitcount than the second memory. The second memory has a greater accessibleupper limit count than the third memory. Note that the accessible upperlimit count is a statistically expected value and does not mean that therelationship is always guaranteed. In addition, the first memory mayhave a faster data transfer speed (access speed) than the second memory.

In the present embodiment, the first memory is assumed to be a volatilesemiconductor memory 8. As the volatile semiconductor memory 8, forexample, a memory commonly used in a computer as the main memory such asa DRAM (Dynamic Random Access Memory), FPM-DRAM, EDO-DRAM, or SDRAM isused. A nonvolatile semiconductor memory such as an MRAM (MagnetoresistRandom Access Memory) or FeRAM (Ferroelectric Random Access Memory) mayalso be adopted if accessed at high speed just as fast as the DRAM withessentially no accessible upper limit count.

The second memory is assumed to be the nonvolatile semiconductor memory9. As the nonvolatile semiconductor memory 9, for example, an SLC(Single Level Cell)-type NAND flash memory is used. When compared withan MLC (Multi Level Cell), the SLC can be read and written into fasterand has higher reliability. However, the SLC has higher bit costs thanthe MLC and is not suitable for increased capacities.

The third memory is assumed to be the nonvolatile semiconductor memory10. As the nonvolatile semiconductor memory 10, for example, an MLC-typeNAND flash memory is used. When compared with the SLC, the MLC can beread and written into more slowly and has lower reliability. However,the MLC has lower bit costs than the SLC and is suitable for increasedcapacities.

In the present embodiment, the nonvolatile semiconductor memory 9 is anSLC-type NAND flash memory and the nonvolatile semiconductor memory 10is an MLC-type NAND flash memory, but, for example, the nonvolatilesemiconductor memory 9 may be a 2-bit/Cell MLC-type NAND flash memoryand the nonvolatile semiconductor memory 10 may be a 3-bit/Cell MLC-typeNAND flash memory.

Reliability means the degree of resistance to an occurrence of datacorruption (durability) when data is read from a storage device.Durability of the SLC is higher than durability of the MLC. Highdurability means a greater accessible upper limit count and lowerdurability means a smaller accessible upper limit count.

The SLC can store 1-bit information in one memory cell. On the otherhand, the MLC can store 2-bit information or more in one memory cell.That is, the mixed main memory 2 according to the present embodiment hasdecreasing order of durability of the volatile semiconductor memory 8,the nonvolatile semiconductor memory 9, and the nonvolatilesemiconductor memory 10.

When compared with the volatile semiconductor memory 8, the nonvolatilesemiconductor memories 9, 10 such as NAND flash memories are cheap andcan be increased in capacity. As the nonvolatile semiconductor memories9, 10, instead of NAND flash memories, for example, other kinds of flashmemory such as NOR flash memories, PRAM (Phase change memory), or ReRAM(Resistive Random access memory) can be used.

Incidentally, an MLC may be adopted as the third memory and an MLC inwhich a pseudo SLC mode that writes data by using only lower pages ofthe MLC may be adopted as the second memory. In this case, the secondmemory and the third memory can be configured by a common chip only,which is advantageous in terms of manufacturing costs.

Comparison of a case when the nonvolatile semiconductor memories 9, 10are used as the main memory and a case when the nonvolatilesemiconductor memories 9, 10 are used as the secondary storage deviceshows that the frequency of access to the nonvolatile semiconductormemories 9, 10 increases when the nonvolatile semiconductor memories 9,10 are used as the main memory. In the present embodiment, theinformation processing device including the mixed main memory 2 formedby mixing the volatile semiconductor memory 8, the nonvolatilesemiconductor memory 9 of SLC, and the nonvolatile semiconductor memory10 of MLC as a main memory is realized. The mixed main memory 2 is aheterogeneous main memory in which arrangement of data is managed by thememory management device 1.

The memory usage information 11, the memory specific information 12, theaddress conversion information 13, and the coloring table 14 are storedin predetermined regions of the nonvolatile semiconductor memories 9,10.

The memory usage information 11 includes the number of times of writingoccurrences and the number of times of reading occurrences of each pageregion of the nonvolatile semiconductor memories 9, 10, the number oftimes of erasure of each block region, and the size of the region beingused.

The memory specific information 12 includes the memory size of thevolatile semiconductor memory 8, the memory sizes of the nonvolatilesemiconductor memories 9, 10, the page sizes and block sizes of thenonvolatile semiconductor memories 9, 10, and the accessible upper limitcounts (the writable upper limit count, readable upper limit count, anderasable upper limit count) of each region. The page size is the unit ofdata size for writing into or reading from the nonvolatile semiconductormemories 9, 10. The block size is the unit of data erasure size of thenonvolatile semiconductor memories 9, 10. In the nonvolatilesemiconductor memories 9, 10, the block size is larger than the pagesize.

The address conversion information 13 is information used to convert alogical address provided by the processors 3 a, 3 b, 3 c into a physicaladdress corresponding to the logical address. Details of the addressconversion information 13 will be described later.

The coloring table 14 is a table to hold coloring information for eachpiece of data. The coloring information includes static colorinformation and dynamic color information. Details thereof will bedescribed later.

Next, the memory management device according to the present embodimentand an operating system will further be described with reference to FIG.2. FIG. 2 is a block diagram showing an example of the configuration ofthe memory management device 1 and the information processing device 100according to the present embodiment. In FIG. 2, the processor 3 b of theprocessors 3 a, 3 b, 3 c in FIG. 1 is selected as the processor to bedescribed, but the description that follows also applies to the otherprocessors 3 a, 3 c.

An operating system 27 is executed by the processor 3 b. The operatingsystem 27 is executed by the processor 3 b and has a right to access thecoloring table 14 stored in the information storage unit 17.

The processing unit 15 of the memory management device 1 includes anaddress management unit 18, a reading management unit 19, a writingmanagement unit 20, a coloring information management unit 21, a memoryusage information management unit 22, and a relocation unit 23. Further,the coloring information management unit 21 includes an access frequencycalculation unit 24 and a dynamic color information management unit 25.

The processing unit 15 performs various kinds of processing based oninformation stored in the information storage unit 17 while using theworking memory 16.

The working memory 16 is used, for example, as a buffer and is used as aworking region for various data conversions and the like.

The functional blocks included in the processing unit 15 can be realizedby one of hardware and software (for the example, the operating system27, firmware or the like) or a combination of both. Whether thefunctional blocks are realized as hardware or software depends on theconcrete embodiment or design limitations imposed on the wholeinformation processing device 100. A person skilled in the art canrealize these functions by various methods for each concrete embodimentand determining such an embodiment is included in the scope of thepresent invention. This also applies to the functional blocks used inthe description that follows.

The address management unit 18 allocates a physical address to a logicaladdress and stores the allocated physical address and the logicaladdress into the address conversion information 13. Accordingly, theprocessing unit 15 can acquire a physical address corresponding to alogical address with reference to the address conversion information 13.

The reading management unit 19 manages read processing of read targetdata to be read from the mixed main memory 2 when the processors 3 a, 3b, 3 c issue a reading request.

The writing management unit 20 manages write processing of write targetdata into the mixed main memory 2 when the processors 3 a, 3 b, 3 cissue a writing request.

The coloring information management unit 21 manages the coloring table14.

The memory usage information management unit 22 manages the memory usageinformation 11 of the mixed main memory 2.

The relocation unit 23 relocates data arranged at a physical addresscorresponding to any logical address based on coloring informationincluded in the coloring table 14 asynchronously to the operations ofthe processors 3 a, 3 b, 3 c. The relocation unit 23 periodicallyrelocates data included in the nonvolatile semiconductor memory 10 whosereading frequency or writing frequency is high into the nonvolatilesemiconductor memory 9 based on, for example, dynamic color informationdescribed later. Also, the relocation unit 23 periodically relocatesdata included in the nonvolatile semiconductor memory 9 whose readingfrequency or writing frequency is low into the nonvolatile semiconductormemory 10 based on, for example, the dynamic color information.Similarly, the relocation unit 23 can relocate data between the volatilesemiconductor memory 8 and the nonvolatile semiconductor memories 9, 10.Write processing by the writing management unit 20 described laterrelocates data by performing determination processing of a writingdestination memory region and determination processing of a writingdestination block region each time an update of data occurs. Incontrast, the relocation unit 23 periodically relocates data. When therelocation unit 23 relocates data, the writing management unit 20 andthe reading management unit 19 do not operate until the relocation iscomplete. The trigger of starting the operation of the relocation unit23 may be a period set by the developer or the period that can be setthrough the user interface. The relocation unit 23 may operate when theinformation processing device 100 pauses.

The access frequency calculation unit 24 calculates access frequencyinformation (a dynamic writing frequency DR_color and a dynamic readingfrequency DR_color) of data based on coloring information included inthe coloring table 14.

The dynamic color information management unit 25 manages dynamic colorinformation included in the coloring table 14.

Next, a mixed main memory according to the present embodiment will bedescribed with reference to FIG. 3. FIG. 3 is a diagram showing anexample of a memory map of the mixed main memory 2 according to thepresent embodiment.

The mixed main memory 2 includes the volatile semiconductor memory 8(DRAM region), the nonvolatile semiconductor memory 9 (SLC region), andthe nonvolatile semiconductor memory 10 (2-bit/Cell region, 3-bit/Cellregion, 4-bit/Cell region). The 2-bit/Cell region, 3-bit/Cell region,and 4-bit/Cell region constitute an MLC region. The DRAM region, SLCregion, 2-bit/Cell region, 3-bit/Cell region, and 4-bit/Cell region arecalled a memory region by the gross.

The volatile semiconductor memory 8 is composed of, for example, a128-Mbyte DRAM region.

The nonvolatile semiconductor memory 9 is composed of, for example, a2-Gbyte B region, a 128-Mbyte B redundant block region, a 2-Gbyte Cregion, and a 128-Mbyte C redundant block region. Each memory region ofthe nonvolatile semiconductor memory 9 is an SLC-type NAND flash memory.

The nonvolatile semiconductor memory 10 is composed of, for example, a2-bit/Cell region composed of a 4-Gbyte A region and a 128-Mbyte Aredundant block region, a 3-bit/Cell region composed of a 4-Gbyte Dregion and a 128-Mbyte D redundant block region, and a 4-bit/Cell regioncomposed of a 4-Gbyte E region and a 128-Mbyte E redundant block region.Each memory region of the nonvolatile semiconductor memory 10 is anMLC-type NAND flash memory. As shown in FIG. 3, a physical address isallocated to each memory region.

If the mixed main memory 2 is configured as described above, the memoryspecific information 12 includes 1) the memory size of the volatilesemiconductor memory 8 (DRAM region) in a memory space of the mixed mainmemory 2, 2) the memory sizes of the nonvolatile semiconductor memories9, 10 in the memory space of the mixed main memory 2, 3) the block sizeand page size of the NAND flash memory constituting the memory space ofthe mixed main memory 2, 4) memory space information (containing theerasable upper limit count, readable upper limit count, and writableupper limit count) allocated as an SLC region (binary region) in thenonvolatile semiconductor memory 9, 5) memory space information(containing the erasable upper limit count, readable upper limit count,and writable upper limit count) allocated to the 2-bit/Cell region, 6)memory space information (containing the erasable upper limit count,readable upper limit count, and writable upper limit count) allocated tothe 3-bit/Cell region, and 7) memory space information (containing theerasable upper limit count and readable upper limit count) allocated tothe 4-bit/Cell region.

Next, the address conversion information (address conversion table) 13according to the present embodiment will be described with reference toFIG. 4. FIG. 4 is a diagram showing an example of the address conversioninformation 13 according to the present embodiment.

In the address conversion information 13, the logical address, physicaladdress of the volatile semiconductor memory 8, physical address of thenonvolatile semiconductor memories 9, 10, and valid/invalid flag aremanaged in tabular form.

In each entry of the address conversion information 13, a logicaladdress, at least one of physical addresses of the volatilesemiconductor memory 8 and the nonvolatile semiconductor memories 9, 10corresponding to the logical address, and the valid/invalid flag areregistered.

The valid/invalid flag is information indicating whether or not eachentry is valid. 1 of the valid/invalid flag indicates valid and 0 of thevalid/invalid flag indicates invalid. The initial value of thevalid/invalid flag of each entry is 0. An entry whose valid/invalid flagis 0 is an entry to which no logical address is mapped or an entry whoselogical address is erased after being mapped thereto. An entry whosevalid/invalid flag is 1 has a logical address mapped thereto and aphysical address corresponding to the logical address is present atleast in one of the volatile semiconductor memory 8 and the nonvolatilesemiconductor memories 9, 10.

In the example of the address conversion information 13 shown in FIG. 4,the logical address, the physical address of the volatile semiconductormemory 8, and the physical address of the nonvolatile semiconductormemories 9, 10 are managed by one entry of the address conversioninformation 13. However, the logical address and the physical address ofthe volatile semiconductor memory 8 may be managed by the addressconversion information 13 so that the logical address and the physicaladdress of the nonvolatile semiconductor memories 9, 10 are managed byanother tag RAM. In this case, when a logical address is converted intoa physical address, the tag RAM is first referenced and if no physicaladdress corresponding to the logical address is found in the tag RAM,the address conversion information 13 is referenced.

Next, the coloring table 14 according to the present embodiment will bedescribed with reference to FIG. 5. FIG. 5 is a diagram showing anexample of the coloring table 14 according to the present embodiment.

In the present embodiment, coloring information is provided for eachpiece of data. The unit of data size of data to which coloringinformation is provided is, for example, the minimum unit of reading andwriting. For example, the minimum unit of reading and writing is thepage size of a NAND flash memory. The coloring table 14 associatescoloring information for each piece of data and stores the coloringinformation in units of entry. An index is attached to each entry of thecoloring table 14. The index is a value generated based on a logicaladdress. When a logical address specifying data is given to the readingmanagement unit 19, the writing management unit 20, the coloringinformation management unit 21, the relocation unit 23, and so forth ofthe memory management device 1, the entry managed by the indexcorresponding to the logical address is referenced to acquire coloringinformation of the data.

The coloring information includes static color information and dynamiccolor information. The static color information is information generatedbased on property of the data to which the coloring information isattached and is a kind of hint information offering a hint to determinean arrangement (writing) region of the data in the mixed main memory 2.The dynamic color information is information containing at least one ofthe number of times and the frequency of reading and writing data. Thedynamic color information may be used as hint information.

Next, static color information will be described with reference to FIG.6. FIG. 6 is a diagram illustrating an example of static colorinformation according to the present embodiment.

The static color information includes at least one piece of informationof “importance”, “reading frequency/writing frequency”, and “data life”of the data. The reading frequency described with reference to FIG. 6corresponds to a static reading frequency described later and thewriting frequency corresponds to a static writing frequency.

“Importance” is a value set by estimating the importance of data basedon the type of the data or the like.

“Reading frequency/writing frequency” is a value set by estimating thefrequency with which data is read or written based on the type of thedata or the like.

“Data life” is a value set by estimating a period (data life) in whichdata is used without being erased based on the type of the data or thelike.

“Importance”, “reading frequency/writing frequency”, and “data life” areestimated from, for example, a property of a file held by a file systemor a property of a region temporarily used for a program.

A property of a file held by a file system is a property determinedbased on a data attribute added to the file of file data containing thedata to which coloring information is attached. A Data attribute addedto the file include header information of the file, a file name, a fileposition, or file management data (information held in inodd). If, forexample, the file is positioned in the Trash of the file system as thefile position, it is estimated that the importance of the property ofdata contained in the file is low, the reading frequency/writingfrequency is low, and the data life is short. Based on the property, alow writing frequency, a low reading frequency, and a short data lifeare estimated for coloring information of the data.

A property of a region temporarily used for a program includes aproperty determined based on the data type when program execution of aprogram in which the data to which coloring information is attached ishandled and a property determined based on the data type when generationof a program file.

The data type when program execution is the data type classified basedon, for example, which region of a stack region, a heap region, and atext region the data is mapped to when program execution. For example, aproperty of data mapped to the stack region or heap region are estimatedthat the writing frequency is high, the reading frequency is high, theimportance is high, and the data life is short. Based on the property, ahigh writing frequency, a high reading frequency, high importance, and ashort data life are estimated for static coloring information of thedata. For example, A property of data mapped to the text region areestimated that the writing frequency is low, the reading frequency ishigh, the importance is high, and the data life is long because the datais read-only data. Based on the property, a high writing frequency, ahigh reading frequency, high importance, and a long data life areestimated for static coloring information of the data.

The data type estimation when generation of a program file is toestimate the importance, reading frequency, and writing frequency ofdata handled by a program when the program is generated.

The static color information may be directly set by the user through theuser interface.

Next, an example of write processing of data based on coloringinformation will be shown with reference to FIG. 7. FIG. 7 is a flowchart showing an example of data arrangement processing.

In the present embodiment, as described above, the mixed main memory 2includes the volatile semiconductor memory 8 and the nonvolatilesemiconductor memories 9, 10. When data is arranged in the mixed mainmemory 2, the memory region of the volatile semiconductor memory 8 orthe nonvolatile semiconductor memories 9, 10 is determined as anarrangement destination.

First, when a writing request of data (write target data) occurs, thewriting management unit 20 references coloring information attached tothe write target data (step S1).

Next, the writing management unit 20 references “data life” of thecoloring information to determine the data life of the write target data(step S2).

If the data life of the write target data is determined to be short(step S3), the writing management unit 20 selects the volatilesemiconductor memory 8 as a memory region in which the write target datais arranged (step S4) and determines the memory region in which thewrite target data is arranged in favor of the volatile semiconductormemory 8 (step S12).

If the data life of the write target data is determined to be long (stepS3), the writing management unit 20 references “importance” of thecoloring information of the write target data to determine theimportance of the write target data (step S5).

If the importance of the write target data is determined to be high(step S6), the writing management unit 20 selects the nonvolatilesemiconductor memory 9 with high durability (reliability) as a memoryregion in which the write target data is arranged (step S7). Further,the writing management unit 20 determines whether to cache the writetarget data in the volatile semiconductor memory 8 based on the coloringinformation of the write target data (cache method based on coloringinformation) (step S8) and determines the nonvolatile semiconductormemory 9 as the memory region in which the write target data is arranged(step S12).

If the importance of the write target data is determined to be low (stepS6), the writing management unit 20 selects the nonvolatilesemiconductor memory 10 with low durability as a memory region in whichthe write target data is arranged (step S9). Further, the writingmanagement unit 20 determines the reading frequency and the writingfrequency of the write target data based on the coloring information(dynamic color information, static color information) of the writetarget data (step S10).

If the reading frequency and the writing frequency of the write targetdata are determined to be high (step S11), the writing management unit20 selects the nonvolatile semiconductor memory 9 as a memory region inwhich the write target data is arranged (step S7). Further, the writingmanagement unit 20 determines whether to cache the write target data inthe volatile semiconductor memory 8 based on the coloring information ofthe write target data (cache method based on coloring information) (stepS8) and determines the nonvolatile semiconductor memory 9 as the memoryregion in which the write target data is arranged (step S12).

If the reading frequency and the writing frequency of the write targetdata are determined to be low (step S11), the writing management unit 20determines whether to cache the write target data in the volatilesemiconductor memory 8 based on the coloring information of the writetarget data (cache method based on coloring information) (step S8) anddetermines the nonvolatile semiconductor memory 10 as the memory regionin which the write target data is arranged (step S12).

Next, a configuration example of the coloring table 14 according to thepresent embodiment will be described with reference to FIG. 8. FIG. 8 isa diagram showing an example of the configuration of the coloring table14 according to the present embodiment. In the coloring table 14 shownin FIG. 8, a case when particularly the reading frequency, writingfrequency, and data life of the coloring information shown in FIGS. 5and 6 are used as the coloring information will be described.

As the coloring information, one of “importance”, “readingfrequency/writing frequency”, and “data life” may be used, any two maybe combined, or all may be combined. Further, other coloring informationthat is not shown in FIG. 6 may be separately defined and used.

The coloring table 14 is a table that associates coloring informationwith each piece of data and holds the coloring information in units ofentry. The data size of data associated with the coloring information bythe coloring table 14 is, for example, the minimum unit of reading orwriting. For example, the minimum data size of reading or writing is thepage size of a NAND flash memory. It is assumed below that the data sizeof data associated with the coloring information by the coloring table14 is the page size, but the present embodiment is not limited to suchan example.

An index is attached to each entry of the coloring table 14.

Coloring information held by the coloring table 14 includes static colorinformation and dynamic color information.

The index is a value generated based on a logical address. When alogical address specifying data is given to the reading management unit19, the writing management unit 20, the coloring information managementunit 21, the relocation unit 23, and so forth of the memory managementdevice 1, the entry managed by the index corresponding to the logicaladdress is referenced to acquire coloring information of the data.

The static color information includes a value SW_color indicating thestatic writing frequency, SR_color indicating the static readingfrequency, a data life SL_color, a time ST_color at which data isgenerated.

The static writing frequency SW_color is a value set by estimating thefrequency with which data is written based on the type of the data orthe like. The static reading frequency SR_color is a value set byestimating the frequency with which data is read based on the type ofthe data or the like. For example, an increasing value is set to thestatic writing frequency SW_color with estimated data having anincreasing writing frequency. For example, an increasing value is set tothe static reading frequency SR_color with estimated data having anincreasing reading frequency.

The data life SL_color is a value set by estimating a period (data life)in which data is used without being erased based on the type of the dataor the like.

The static color information is a statically predetermined value by aprogram (process) that generates data. The operating system 27 executedin the information processing device 100 may predict static colorinformation based on a file extension, a file header of data, or thelike.

The dynamic color information includes a writing count DWC_color of dataand a reading count DRC_color of data. The writing count DWC_color ofdata is the number of times the data is written into the mixed mainmemory 2. The reading count DRC_color of data is the number of times thedata is read from the mixed main memory 2. The dynamic color informationmanagement unit 25 manages for each piece of data the number of timesthe data is written into the mixed main memory 2 based on the writingcount DWC_color. The dynamic color information management unit 25manages for each piece of data the number of times the data is read fromthe mixed main memory 2 based on the reading count DRC_color. Asdescribed above, the mixed main memory 2 is used as a main memory. Thus,data processed by the processors 3 a, 3 b, 3 c is written into the mixedmain memory 2 or read from the mixed main memory 2. The dynamic colorinformation management unit 25 increments the writing count DWC_color ofdata each time the data is written. The dynamic color informationmanagement unit 25 also increments the reading count DWC_color of dataeach time the data is read.

As will be described later, the access frequency calculation unit 24calculates the dynamic writing frequency DW_color from the writing countDWC_color of data. The access frequency calculation unit 24 calculatesthe dynamic reading frequency DR_color from the reading count DRC_colorof data.

The dynamic writing frequency DW_color is a value indicating thefrequency with which the data is written into the mixed main memory 2.The dynamic reading frequency DR_color is a value indicating thefrequency with which the data is read from the mixed main memory 2. Thecalculation method of the dynamic writing frequency DW_color and thedynamic reading frequency DR_color will be described later.

As will be described later, when a writing request or a reading requestoccurs from the processors 3 a, 3 b, 3 c to the mixed main memory 2, thememory management device 1 determines the write region, reading methodand the like by referencing coloring information.

Next, static color information according to the present embodiment willbe described with reference to FIGS. 9 and 10. FIG. 9 is a diagramshowing a first example of a setting of static color information (thestatic writing frequency SW_color, the static reading frequencySR_color, and the data life SW_color) to various kinds of data. FIG. 10is a diagram showing a second example of a setting of static colorinformation (the static writing frequency SW_color, the static readingfrequency SR_color, and the data life SR_color) to various kinds ofdata.

The reading frequency of the text region of a kernel is normally highand the writing frequency thereof is low. The operating system 27 setsthe static reading frequency SR_color of the text region in which theoperating system 27 operates to 5 and the static writing frequencySW_color to 1. The operating system 27 predicts that the data lifeSL_color of the text region of the kernel is long.

On the other hand, both the reading frequency and the writing frequencyof the data region of the kernel are normally high. Thus, the operatingsystem 27 sets the static reading frequency SR_color to 5 and the staticwriting frequency SW_color to 5 for the data region of the kernel.

Because the data region dynamically secured in the kernel is deletedwhen data is no longer needed, the data life SL_color is assumed to beSHORT.

The reading frequency of the text region of a user program, whencompared with the kernel reenterably invoked by all processes, is low.However, when a process is active, like the kernel, the readingfrequency is high. Thus, the static writing frequency SW_color is set to1 and the static reading frequency SR_color is set to 4 for the textregion of the user program. The data life SR_color for the text regionof the user program is commonly long because the data life SL_color is aperiod until the program is uninstalled. Thus, the data life SL_colorfor the text region of the user program is set to LONG.

A region dynamically secured for a program is roughly divided into tworegions. One type of the region is data (including the stack region)discarded when execution of a program ends. Such data has the short datalife SR_color and the reading frequency and writing frequency thereofare high. Thus, the static reading frequency SR_color is set to 4 andthe static writing frequency SW_color is set to 4 for data discardedwhen execution of a program ends. Another region dynamically secured forthe program is a region generated by the program for a new file. Datagenerated by the program has the long data life SL_color and the readand write frequencies thereof depend on the type of a generated file.

The data life SL_color of a file is set to be long for data handled as afile to be referenced by a process.

A case when a system file whose file extension is, for example, SYS,dll, DRV and the like is read will be described. Data having such anextension is a file read when the operating system 27 performs variouskinds of processing. When the operating system 27 is installed on themixed main memory 2, data having such an extension is rarely updatedafter being written once. A file having such an extension is predictedthat the access frequency thereof is, among files, relatively high, butwhen compared with the text region of a program (kernel), the accessfrequency thereof is low. Therefore, the operating system 27 sets thestatic writing frequency SW_color having such an extension to 1 and thestatic reading frequency SR_color to 3. This setting shows that thewriting frequency predicted from data is extremely low and the predictedreading frequency is high. That is, data having such an extension ispredicted that the data may be rewritten several times when theoperating system 27 is updated or another program is installed and thusis handled almost like read-only data.

The number of users who use a program to edit an audio file is small.Thus, the frequency of writing music data compressed by, for example,MP3 is considered to be low. The frequency of reading music data isconsidered to be higher than the frequency of writing music data. Thus,the static writing frequency SW_color of music data compressed by MP3 orthe like is set to 1 and the static reading frequency SW_color thereofto 2.

The number of users who use a video editing program is small. Thus, thefrequency of writing video data compressed by, for example, MPEG isconsidered to be low. The frequency of reading video data is consideredto be higher than the frequency of writing video data. Thus, the staticwriting frequency SW_color of video data compressed by MP3 or the likeis set to 1 and the static reading frequency SW_color thereof to 2.

The number of users who use an editing program of text data is large.Thus, for example, the writing frequency and reading frequency of a textfile is considered to be high. Therefore, the static writing frequencySW_color of the text file is set to 3 and the static reading frequencySW_color thereof to 3.

The number of users who use a Web browser is large. Thus, the readingfrequency and writing frequency of a browser cache file are consideredto be equal to or higher than those of a media file of music data orvideo data. Therefore, the static writing frequency SW_color of thebrowser cache file is set to 1 and the static reading frequency SW_colorthereof to 3.

The static writing frequency SW_color of a file arranged in a directorywhose access frequency is low such as the Trash is set to 1 and thestatic reading frequency SW_color thereof to 1.

Photo data whose extension is typically JPEG and movie data whoseextension is typically MOV are rarely rewritten after being writtenonce. The predicted frequency with which such photo data or movie datais accessed from a program is low. Thus, the operating system 27 sets asmall value to the static writing frequency SW_color and the staticreading frequency SR_color of photo data and movie data.

Next, generation processing of the coloring table 14 according to thepresent embodiment will be described with reference to FIG. 11. FIG. 11is a flow chart showing an example of generation processing of thecoloring table 14. The coloring table 14 is generated when the system isinitially activated. The coloring table 14 is arranged in any region ofthe nonvolatile semiconductor memories 9, 10. The address at which thecoloring table 14 is arranged may be determined by the implementation ofthe memory management device 1.

In step T1, the information device 100 is turned on and activated.

In step T2, the coloring information management unit 21 converts a baseaddress of the coloring table 14 to a logical address and generates anindex for each piece of data.

In step T3, the coloring information management unit 21 sets the baseaddress of the coloring table 14 to the information storage unit 17. Theinformation storage unit 17 is composed of, for example, registers. Thebase address of the coloring table 14 is set to, for example, a coloringtable register.

Next, generation processing of an entry of the coloring table 14according to the present embodiment will be described with reference toFIG. 12. FIG. 12 is a flow chart showing an example of generationprocessing of an entry of the coloring table 14.

The processors 3 a, 3 b, 3 c secure regions in a logical address spaceused for executing the processes 6 a, 6 b, 6 c. When a region in thelogical address space is secured, 0 is set to the valid/invalid flag ofthe address conversion information 13 of the secured logical address. Aphysical address is allocated to the logical address when the processes6 a, 6 b, 6 c access (read or write) the secured logical address withinthe range of the logical address space. When a physical address isallocated to the logical address, static color information for the datacorresponding to the logical address is registered with the coloringtable 14 and also 1 is set to the valid/invalid flag of the addressconversion information 13 of the logical address.

First, the processes 6 a, 6 b, 6 c executed by the processors 3 a, 3 b,3 c issue a request to secure a region in the logical address space toarrange new data (step U1). Unused regions in the logical address spaceare managed by the operating system 27 and the logical address isdetermined by the operating system 27 (step U2).

Next, when new data is generated by the processes 6 a, 6 b, 6 c, theoperating system 27 generates static color information based on the typeof the newly generated data or the like (step U3). The static colorinformation is generated for each page size of the generated data. If,for example, the data size of the generated data is larger than the pagesize, the data is divided into the page size and static colorinformation is generated for each divided page size. It is assumed belowthat the data size of the write target data is equal to the page size,but the present embodiment is not limited to such an example.

Next, the operating system 27 references the coloring table 14 based onthe base address set to the information storage unit 17 (step U4).

Next, the operating system 27 registers the generated static colorinformation with an entry of the coloring table 14 to which the indexcorresponding to the secured logical address is attached (step U5).

After the logical address space being successfully secured by theoperating system 27, the processes 6 a, 6 b, 6 c executed by theprocessors 3 a, 3 b, 3 c issue a reading request or writing request tothe secured logical address space. At this point, the address managementunit 18 determines the physical address for the logical address to whichdata is written and this processing will be described later.

When, with the processing described above, new data is generated andwritten into the mixed main memory 2 after the processes 6 a, 6 b, 6 cbeing executed by the processors 3 a, 3 b, 3 c, coloring information isgenerated for the newly generated data and registered with a new entryof the coloring table 14. Accordingly, new data can be written into themixed main memory 2.

Next, the alignment of entries of the coloring table 14 will bedescribed with reference to FIGS. 13 and 14. FIG. 13 is a diagramshowing a first example of an alignment of entries of the coloring table14. FIG. 14 is a diagram showing a second example of an alignment ofentries of the coloring table 14.

Entries of the coloring table 14 are compatible with the minimum readsize of data (for example, the page size of a NAND flash memory), butthe processes 6 a, 6 b, 6 c are not forced to map after entries beingaligned to the minimum read size of data when data is mapped to thelogical address space. Thus, there is the possibility that a pluralityof pieces of data corresponds to one entry of the coloring table 14.

In such a case, as shown in FIG. 13, the operating system 27 causes,among the plurality of pieces of data corresponds to one entry, the datawhose reading frequency and writing frequency are estimated to be thehighest to represent.

Alternatively, as shown in FIG. 14, the operating system 27 setsweighted average values of the static writing frequency SW_color and thestatic reading frequency SR_color of each piece of data with the size ofdata occupying one entry set a weight.

The static writing frequency SW_color and the static reading frequencySR_color shown in the coloring table 14 are embedded in source code suchas the operating system 27 by a program developer or predicted by theoperating system 27. However, a file or photo data may be used foranother purpose than intended by the program developer. Generally, datasuch as photo data is accessed almost exclusively for reading andcontent of photo data is rarely rewritten. However, when a program toprocess photo data processes specific photo data, the photo data beingprocessed may frequently be rewritten. In such a case, if the staticwriting frequency SW_color and the static reading frequency SR_color ofthe coloring table 14 can be rewritten by the user, a specific file canbe moved to a region that allows for a more number of times of rewriteat a higher speed.

To realize such an operation, it is preferable to design the file systemof the operating system 27 so that coloring information of each piece ofdata can be rewritten by software of the operating system 27. Forexample, it is preferable to design the information processing device100 in such a way that An attribute corresponding to the coloring table14 can be viewed on the GUI screen by opening property of a file by acommon browser and to design the operating system 27 so that initialdata thereof can be changed by the user on the GUI.

Next, the method of calculating the dynamic writing frequency DW_colorand the dynamic reading frequency DR_color based on dynamic colorinformation and static color information will be described withreference to FIG. 15. FIG. 15 is a diagram showing an example of themethod of calculating the dynamic writing frequency DR_color and thedynamic reading frequency DR_color based on dynamic color informationand static color information. In FIG. 15, the horizontal axis representsthe time and the vertical axis represents the number of times of access(the reading count DWC_color or the writing count DRC_color).

If new data is generated at a data generation time, coloring information(including the data generation time) is generated for the newlygenerated data and registered with a new entry of the coloring table 14and then, the data is written into the mixed main memory 12. With anoccurrence of access (read or write) to the data after the datageneration time, the number of times of access (the writing countDWC_color and the reading count DRC_color) increases with the passage oftime. The number of times of access is increased by the dynamic colorinformation management unit 25. The access frequency calculation unit 24of the memory management device 1 calculates the dynamic writingfrequency DW_color and the dynamic reading frequency DR_color based onthe number of times of access.

The writing count DWC_color of the data and the reading count DRC_colorof the data at the current time can be determined by referencing thecoloring table 14. The dynamic writing frequency DW_color at the currenttime is determined by a time average (average rate of change a) of thewriting count DWC_color from the data generation time ST_color to thecurrent time. The dynamic reading frequency DR_color at the current timeis determined by a time average (average rate of change a) of thereading count DRC_color from the data generation time ST_color to thecurrent time. Accordingly, the dynamic writing frequency DW_color andthe dynamic reading frequency DR_color of the data are calculated basedon the dynamic color information (the writing count DWC_color and thereading count DRC_color).

Next, high or low of the frequency of access to the data is determinedbased on the calculated dynamic writing frequency DW_color and dynamicreading frequency DR_color. High or low of frequency of access isdetermined based on, for example, the memory specific information 11 ofthe mixed main memory 2 into which the data is written and thecalculated dynamic writing frequency DW_color and dynamic readingfrequency DR_color.

In FIG. 15, “accessible upper limit count×weight 1/data life” is set asthe inclination of Formula A and “accessible upper limit count×weight2/data life” is set as the inclination of Formula B, where weight1>weight 2 holds. Weight 1 and weight 2 can arbitrarily be set inaccordance with the mixed main memory 2 into which the data from whichthe dynamic writing frequency DW_color and the dynamic reading frequencyDR_color are calculated is written.

If the average rate of change α<the inclination of Formula A holds, thedynamic access frequency of the data is determined to be high.

If the inclination of Formula B<the average rate of change α≦theinclination of Formula A holds, the dynamic access frequency of the datais determined to be medium.

If the average rate of change α≦the inclination of Formula B holds, thedynamic access frequency of the data is determined to be low.

Next, processing to read data from the mixed main memory 2 will bedescribed with reference to FIG. 16. FIG. 16 is a flow chart showing anexample of the processing to read the data.

First, the processes 6 a, 6 b, 6 c executed by the processors 3 a, 3 b,3 c cause a reading request of data (read target data) (step W1).

Next, a virtual address specifying the read target data is convertedinto a logical address based on a page table (not shown) included in theprocessors 3 a, 3 b, 3 c (step W2).

Next, the reading management unit 19 references the valid/invalid flagof the entry of the logical address corresponding to the read targetdata of the address conversion information 13 (step W3).

If the valid/invalid flag of the address conversion information 13 is 0(step W3 a), data is undefined because writing for the logical addresshas not occurred at once. In this case, the reading management unit 19behaves as if to read 0 data for the size of the reading request (stepW8) before proceeding to processing in step W10.

If the valid/invalid flag of the address conversion information 13 is 1(step W3 a), data writing for the logical address has occurred at leastonce. In this case, the reading management unit 19 references theaddress conversion information 13 to determine whether datacorresponding to the logical address is stored in the volatilesemiconductor memory 8 (step W4).

If the reading management unit 19 determines that data corresponding tothe logical address is stored in the volatile semiconductor memory 8(step W4 a), the processing proceeds to step W10 to read the data fromthe volatile semiconductor memory 8.

If the reading management unit 19 determines that data corresponding tothe logical address is not stored in the volatile semiconductor memory 8(step W4 a), the reading management unit 19 determines the method ofreading the read target data from the nonvolatile semiconductor memories9, 10 by referencing the coloring table 14 (step W5). Decisionprocessing of the reading method will be described later.

Next, the reading management unit 19 determines whether the read targetdata needs to be moved (rewritten) by referencing the memory specificinformation 11 and the memory usage information 12 of the nonvolatilesemiconductor memories 9, 10 in which the read target data is stored(step W6).

If the reading management unit 19 determines that the read target datadoes not need to be moved (step W6 a), the processing proceeds to stepW9.

If the reading management unit 19 determines that the read target dataneeds to be moved (step W6 a), the reading management unit 19 moves theread target data to another region of the nonvolatile semiconductormemories 9, 10 (step W7) and then the processing proceeds to step W9.

In step W9, the memory usage information management unit 22 incrementsthe reading count of the memory usage information 11 when data is readfrom a nonvolatile memory region. In step W10, the dynamic colorinformation management unit 25 increments the reading count DRC_color ofdata of the coloring table 14 when the data is read. In step W11, thereading management unit 19 reads data based on a physical addressobtained from a logical address and the address conversion information13.

Next, decision processing of the reading method of data will bedescribed with reference to FIG. 17. FIG. 17 is a flow chart showing anexample of decision processing of the reading method of data. Thedecision processing of the reading method is processing to determinewhether to use a memory region of the volatile semiconductor memory 8 asa cache when data is read from a memory region of the nonvolatilesemiconductor memories 9, 10. This processing corresponds to step W5 inFIG. 16.

The mixed main memory 2 includes, as described above, the volatilesemiconductor memory 8 and the nonvolatile semiconductor memories 9, 10.In the present embodiment, a portion of the volatile semiconductormemory 8 can be used as a cache memory. When data is read from thenonvolatile semiconductor memories 9, 10 of the mixed main memory 2,data whose reading frequency is high is read after being cached in thevolatile semiconductor memory 8. On the other hand, data whose readingfrequency is low is read directly from the nonvolatile semiconductormemories 9, without being cached in the volatile semiconductor memory 8.

First, the reading management unit 19 references the static readingfrequency SR_color of the read target data by referencing the coloringtable 14 (step V1). If the static reading frequency SR_color is large(for example, SR_color=5) (step V1 a), the processing proceeds to stepV4 to cache the read target data in the volatile semiconductor memory 8(DRAM region) from the nonvolatile semiconductor memories 9, 10.

If the static reading frequency SR_color of the read target data issmall (for example, SR_color<=4) (step V1 a), the reading managementunit 19 checks the region into which the read target data is written byreferencing the address conversion information 13 (step V2) and further,the access frequency calculation unit 24 calculates the dynamic readingfrequency DR_color of the read target data (step V3).

If “SR_color≧3 or DR_color is high” holds for both the static readingfrequency SR_color and the dynamic reading frequency DR_color of theread target data (step V3 a), the reading management unit 19 checkswhether there is free space into which the read target data can bewritten in the volatile semiconductor memory 8 (DRAM region) (step V4).If there is free space in the volatile semiconductor memory 8 (step V4a), the reading management unit 19 caches the read target data in thevolatile semiconductor memory 8 (DRAM region) from the nonvolatilesemiconductor memories 9, 10 (step V5). If there is no free space in thevolatile semiconductor memory 8 (step V4 a), the reading management unit19 secures free space by writing data stored in the volatilesemiconductor memory 8 back to the nonvolatile semiconductor memories 9,10 to erase the data stored in the volatile semiconductor memory 8 (stepV6). After the write-back processing, the reading management unit 19checks for free space of the volatile semiconductor memory 8 again (stepV7). The processing proceeds to step V5 if free space is present in thevolatile semiconductor memory 8 (step V7 a) and the processing proceedsto step V8 if free space is not present in the volatile semiconductormemory 8 (step V7 a).

If “SR_color≧3 or DR_color is high” does not hold for the static readingfrequency SR_color and the dynamic reading frequency DR_color of theread target data (step V3 a), the reading management unit 19 does notcache the read target data in the volatile semiconductor memory 8 andreads the read target data directly from the nonvolatile semiconductormemories 9, 10 (step V8).

The reading method is determined, as described above, by referencing thestatic reading frequency SR_color and the dynamic reading frequencyDR_color.

In FIG. 17, a determination of the data life SL_color is not executed.The reason therefor will be described. As will be described later, datawhose data life SL_color is short is arranged in the volatilesemiconductor memory 8 when the data is written. Thus, data whosevalid/invalid flag is 1 and whose data life SL_color indicates a shortlife will be stored in the volatile semiconductor memory 8. As a result,the determination based on the data life SL_color is not needed in FIG.17.

Next, the reading method of data shown in FIGS. 9 and 10 will bedescribed more concretely. The reading method of the data shown in FIGS.9 and 10 is determined as described below by following the flow chart ofthe decision processing of the reading method of data illustrated inFIG. 17.

First, a high reading frequency and a low writing frequency areestimated for the text region of the kernel for which 5 is set to thestatic reading frequency SR_color and 1 is set to the static writingfrequency SW_color. First data in the text region of the kernel is readwhen the operating system 27 performs various kinds of processing andthus, the reading count increases and it becomes necessary to read thefirst data still faster.

The memory management device 1 writes the first data read from thenonvolatile semiconductor memories 9, 10 into the secondary cache memory5 b or the primary cache memory 4 b of the processor 3 b and alsotransfers the read first data to the memory region of the volatilesemiconductor memory 8 of the mixed main memory 2 in parallel.

When the same first data is read again, the first data is read from thesecondary cache memory 5 b or the primary cache memory 4 b of theprocessor 3 b or, if no cache hit occurs, from the memory region of thevolatile semiconductor memory 8 of the mixed main memory 2. The firstdata stored in the memory region of the volatile semiconductor memory 8of the mixed main memory 2 is held in the volatile semiconductor memory8 till power-off as long as the memory region of the volatilesemiconductor memory 8 is not exhausted.

Next, the data region of the kernel for which 5 is set to the staticreading frequency SR_color and 5 is set to the static writing frequencySW_color is a region that is newly generated and initialized each timethe system (the information processing device 100) is activated. Thus, asecond data life SL_color in the data region of the kernel is estimatedto be short. The memory management device 1 first references the seconddata life SL_color. Second data is present in the volatile semiconductormemory 8 as long as the memory region of the volatile semiconductormemory 8 is not exhausted and is erased from the volatile semiconductormemory 8 at power-off.

Next, the reading frequency for the region of a user program for which 4is set to the static reading frequency SR_color and 1 is set to thestatic writing frequency SW_color is lower than the reading frequency ofthe kernel that is reenterably invoked by all processes. Third data inthe region of user program is arranged in the memory region of thevolatile semiconductor memory 8, but if the memory region of thevolatile semiconductor memory 8 of the mixed main memory 2 is fullyoccupied, the third data is to be written back from the volatilesemiconductor memory 8 to the memory region of the nonvolatilesemiconductor memories 9, 10. The order of third data to be written backis determined based on information of the coloring table 14. Whenwritten back, the third data is moved from the volatile semiconductormemory 8 to the nonvolatile semiconductor memories 9, 10 in ascendingorder of reading count.

Fourth data whose data life SL_color is set to be short of fourth datain a region for which 4 is set to the static reading frequency SR_colorand 4 is set to the static writing frequency SW_color and which isdynamically secured by a program is present, like in the data region ofthe kernel, in the volatile semiconductor memory 8 as long as the memoryregion of the volatile semiconductor memory 8 is not exhausted and iserased from the volatile semiconductor memory 8 at power-off.

On the other hand, fourth data whose data life SL_color is set to belong is arranged in the memory region of the volatile semiconductormemory 8, but if the memory region of the volatile semiconductor memory8 of the mixed main memory 2 is fully occupied, the fourth data is to bewritten back from the volatile semiconductor memory 8 to the memoryregion of the nonvolatile semiconductor memories 9, 10.

Next, data handled as a file to be referenced by a process will bedescribed. In FIG. 10, the data life SL_color of all data handled as afile to be referenced by the process is set to be long.

An extremely low writing frequency and a high predicted readingfrequency are estimated by the operating system 27 for fifth dataincluded in a file class for which 1 is set to the static writingfrequency SW_color and 3 is set to the static reading frequencySR_color. In this case, the memory management device 1 arranges thefifth data in the memory region of the volatile semiconductor memory 8,but if the memory region of the volatile semiconductor memory 8 of themixed main memory 2 is fully occupied, the fifth data is to be writtenback from the volatile semiconductor memory 8 to the memory region ofthe nonvolatile semiconductor memories 9, 10.

The extremely low static writing frequency SW_color and the lowpredicted static reading frequency SR_color are estimated by theoperating system 27 for sixth data included in a file class for which 1is set to the static writing frequency SW_color and 2 is set to thestatic reading frequency SR_color. If the static reading frequencySR_color is not determined to be high like in this case, the memorymanagement device 1 directly accesses the nonvolatile semiconductormemories 9, 10 without passing through a cache of the volatilesemiconductor memory 8 when reading data.

The extremely low static writing frequency SW_color and the extremelylow predicted static reading frequency SR_color are estimated by theoperating system 27 for seventh data included in a file class for which1 is set to the static writing frequency SW_color and 1 is set to thestatic reading frequency SR_color. If the static reading frequency isnot determined to be high like in this case, the memory managementdevice 1 directly accesses the nonvolatile semiconductor memories 9, 10without passing through a cache of the volatile semiconductor memory 8when reading data.

The reading method of the read target data is determined, as describedabove, based on coloring information of the read target data.Accordingly, the reading method suited to the characteristic of the readtarget data (the static reading frequency SR_color, the static writingfrequency SW_color, and the data life SL_color) can be used, improvingefficiency to read data.

Next, write processing of data into the mixed main memory 2 will bedescribed with reference to FIG. 18. FIG. 18 is a flow chart showing anexample of write processing of data.

First, the processes 6 a, 6 b, 6 c executed by the processors 3 a, 3 b,3 c cause a writing request of data (write target data) (step X1).

Next, a virtual address specifying the write target data is convertedinto a logical address based on a page table (not shown) included in theprocessors 3 a, 3 b, 3 c (step X2).

Next, the writing management unit 20 determines a write target memoryregion of the mixed main memory 2 by referencing the coloring table 14(step X3). The selection of the write target memory region will bedescribed later.

The writing management unit 20 determines whether the write targetmemory selected in step X3 is the volatile semiconductor memory 8 (stepX4). If, as a result of the determination, the selected write targetmemory is the volatile semiconductor memory 8 (step X4 a), processing instep X7 is performed and, if the selected write target memory is anonvolatile semiconductor memory (step X4 a), processing in step X5 isperformed.

In step X5, the writing management unit 20 determines a write targetblock region in the memory region of the nonvolatile semiconductormemories 9, 10 by referencing the memory usage information 11 and thecoloring table 14. In step X6, the address management unit 18 updatesthe address conversion information 13 based on the physical address of apage in the write target block. If the nonvolatile semiconductormemories 9, 10 are NAND flash memories, the same physical address is notoverwritten and thus, an update of the physical address accompanying thewriting is needed.

After the physical address of writing destination is being determined,the writing management unit 20 performs write processing of data (stepX7). Subsequently, the address management unit 18 sets the valid/invalidflag of the address conversion information 13 to 1 (step X8). Thedynamic color information management unit 25 increments the writingcount DWC_color of the coloring table 14 (step X9) and the memory usageinformation management unit 22 increments the writing count of thememory usage information 11 (step X10).

Next, decision processing of the write target memory region of data willbe described with reference to FIG. 19. FIG. 19 is a flow chart showingan example of decision processing of the writing destination region ofdata.

In step Y1, the writing management unit 20 references the data lifeSL_color of the write target data.

In step Y2, the writing management unit 20 determines whether or not thedata life SL_color is longer than a predetermined value. If the datalife SL_color is equal to or longer than the predetermined value, theprocessing proceeds to step Y9.

If the data life is shorter than the predetermined value, in step Y3,the writing management unit 20 checks for free space of the DRAM regionand, in step Y4, the writing management unit 20 determines whether thereis free space in the DRAM region.

If there is free space in the DRAM region, in step Y5, the writingmanagement unit 20 writes the write target data into the DRAM region.

If there is no free space in the DRAM region, in step Y6, the writingmanagement unit 20 performs write-back processing from the DRAM regionto the other nonvolatile semiconductor memory. Then, in step Y7, thewriting management unit 20 checks for free space of the DRAM region and,in step Y8, the writing management unit 20 determines whether there isfree space in the DRAM region.

If there is free space in the DRAM region, the processing returns tostep Y5 and the writing management unit 20 writes the write target datainto the DRAM region.

If there is no free space in the DRAM region, the processing proceeds tostep Y9.

In step Y9, the writing management unit 20 references the static writingfrequency SW_color of the write target data managed by the coloringtable 14.

In step Y10, the writing management unit 20 determines whether 5 is setto the static writing frequency SW_color (whether or not the staticwriting frequency SW_color of the write target data is high).

If 5 is set to the static writing frequency SW_color, the processingproceeds to Y13 and the writing management unit 20 selects the B regionas the writing destination of the write target data.

If a value which is not 5 (value less than 5) is set to the staticwriting frequency SW_color, in step Y11, the memory management device 1references the static reading frequency SR_color of the write targetdata managed by the coloring table 14.

In step Y12, the writing management unit 20 determines to which of 1 to5 the static reading frequency SR_color is set.

If, in step Y12, 5 is set to the static reading frequency SR_color, instep Y13, the writing management unit 20 selects the B region as thewriting destination of the write target data.

If, in step Y12, 4 is set to the static reading frequency SR_color, instep Y14, the writing management unit 20 selects the A region as thewriting destination of the write target data.

If, in step Y12, 3 is set to the static reading frequency SR_color, instep Y15, the writing management unit 20 calculates the dynamic writingfrequency DW_color of the data based on coloring information of thedata. Next, in step Y16, the writing management unit 20 references thestatic writing frequency SW_color of the write target data managed bythe coloring table 14.

In step Y17, the writing management unit 20 determines whether or not“the static writing frequency SW_color is equal to or more than 3 or thedynamic writing frequency DW_color of data is at a high level” holds.

If, in step Y17, “SW_color is equal to or more than 3 or the dynamicwriting frequency DW_color of data is at a high level” does not hold,the processing proceeds to step Y14 and the writing management unit 20selects the A region.

If, in step Y17, “SW_color is equal to or more than 3 or the dynamicwriting frequency DW_color of data is at a high level” holds, theprocessing proceeds to step Y18 and the writing management unit 20selects the C region.

If, in above step Y12, 2 is set to the static reading frequencySR_color, in step Y19, the writing management unit 20 calculates thedynamic writing frequency DW_color of the data based on coloringinformation of the data.

In step Y20, the writing management unit 20 references the staticwriting frequency SW_color of the write target data managed by thecoloring table 14.

In step Y21, the writing management unit 20 determines whether or not“SW_color is equal to or more than 3 or the calculated dynamic writingfrequency DW_color is at a high level” holds.

If, in step Y21, “SW_color is equal to or more than 3 or the calculateddynamic writing frequency DW_color is at a high level” holds, theprocessing proceeds to step Y18 and the writing management unit 20selects the C region.

If, in step Y21, “SW_color is equal to or more than 3 or the calculateddynamic writing frequency DW_color is at a high level” does not hold,the processing proceeds to step Y22.

In step Y22, the writing management unit 20 determines whether or not“SW_color is equal to or more than 2 or the calculated dynamic writingfrequency DW_color is at a medium level” holds.

If, in step Y22, “SW_color is equal to or more than 2 or the calculateddynamic writing frequency DW_color is at a medium level” holds, theprocessing proceeds to step Y23 and the writing management unit 20selects the D region.

If, in step Y22, “SW_color is equal to or more than 2 or the calculateddynamic writing frequency DW_color is at a medium level” does not hold,the processing proceeds to step Y24 and the writing management unit 20selects the E region.

If, in step Y12, 1 is set to the static reading frequency SR_color, instep Y25, the writing management unit 20 calculates the dynamic writingfrequency DW_color of the data based on coloring information of thedata.

In step Y26, the writing management unit 20 references the staticreading frequency SR_color of the write target data managed by thecoloring table 14. Then, the processing returns to step Y21.

In the example of FIG. 19, the writing destination region of data isdetermined by using the static color information and the dynamic colorinformation, but the writing destination region of data may bedetermined by using only static color information. That is, a portion ofthe flow chart in the example of FIG. 19 may be diverted to determinethe writing destination region of data based on the static colorinformation.

For example, the developer of the operating system 27 makes settings asshown in FIGS. 9 and 10 for implementation of the data reading method ofthe reading management unit 19 and the data writing method of thewriting management unit 20.

For example, the number of times the first data is read from the textregion of the kernel for which 5 is set to SR_color and 1 is set toSW_color is estimated to be large and the number of times the first datais written thereinto is estimated to be small. The first data is movedto the volatile semiconductor memory 8 during system operation beforebeing read or written based on the decision operation of the readingmethod shown in FIG. 17. Thus, the frequency with which the first datais actually written into the nonvolatile semiconductor memories 9, 10 islow. However, the importance of the first data is high and thus, in FIG.19, the writing management unit 20 writes the first data into the Bregion of the nonvolatile semiconductor memory 9, which is an SLC.

Next, the data region of the kernel for which 5 is set to SR_color and 5is set to SW_color is a region that is newly generated and initializedeach time the information processing device 100 is activated and thus,the data life of the second data in the data region of the kernel isestimated to be short. The writing management unit 20 first referencesthe data life SL_color of the second data. The second data is alwayspresent in the volatile semiconductor memory 8 during operation of theinformation processing device 100 and is erased from the volatilesemiconductor memory 8 at power-off. Therefore, the second data is notwritten into the nonvolatile semiconductor memories 9, 10.

Next, the reading frequency for the region of the user program for which4 is set to SR_color and 1 is set to SW_color is lower than the readingfrequency of the kernel that is reenterably invoked by all processes.The third data in the region of the user program is written into thememory region of the nonvolatile semiconductor memories 9, 10 only ifnot accessed for a long time by the reading method shown in FIG. 16.Thus, the frequency with which the third data is written into thenonvolatile semiconductor memories 9, 10 is low. The third data is lowin importance when compared with data in the text region of the kerneland so is written into the A region, which is an MLC region in FIG. 19.

The fourth data whose data life SL_color is set to be short of fourthdata in a region for which 4 is set to SR_color and 4 is set to SW_colorand which is dynamically secured by a program is always present, like inthe data region of the kernel, in the volatile semiconductor memory 8during operation of the information processing device 100. The writingmanagement unit 20 first references the data life SL_color of the seconddata. The fourth data is always present in the volatile semiconductormemory 8 during system operation, is erased from the volatilesemiconductor memory 8 at power-off and thus is not written into thenonvolatile semiconductor memories 9, 10.

On the other hand, the fourth data whose data life SL_color is set to belong is arranged in the memory region of the volatile semiconductormemory 8, but if the memory region of the volatile semiconductor memory8 of the mixed main memory 2 is fully occupied, the fourth data is to bewritten back from the volatile semiconductor memory 8 to the memoryregion of the nonvolatile semiconductor memories 9, 10. The text regionof the program is high in importance of data and thus, data in the textregion of the program is written into the C region, which is an SLC.

Next, data handled as a file to be referenced by a process will bedescribed. In FIG. 10, the data life SL_color of all files referenced bythe process is set to be long.

An extremely low writing frequency and a high predicted readingfrequency are estimated by the operating system 27 for the fifth data ina system file class for which 1 is set to SW_color and 3 is set toSR_color. In this case, the writing management unit 20 arranges thefifth data in the memory region of the volatile semiconductor memory 8,but if the memory region of the volatile semiconductor memory 8 of themixed main memory 2 is fully occupied, the fifth data is to be writtenback from the volatile semiconductor memory 8 to the memory region ofthe nonvolatile semiconductor memories 9, 10. The writing frequency ofthe fifth data is determined to be low and thus, the writing managementunit 20 arranges the fifth data in the MLC region.

An extremely high writing frequency and a high predicted readingfrequency are estimated by the operating system 27 for a file class forwhich 3 is set to SW_color and 3 is set to SR_color. Thus, the writingmanagement unit 20 arranges data in the file class for which 3 is set toSW_color and 3 is set to SR_color in the SLC region.

An extremely low writing frequency and a low predicted reading frequencyare estimated by the operating system 27 for the sixth data included ina file class for which 1 is set to SW_color and 2 is set to SR_color.The sixth data is determined to be low in importance as a file and thus,the writing management unit 20 arranges the sixth data in the MLCregion.

An extremely low writing frequency and an extremely low predictedreading frequency are estimated by the operating system 27 for theseventh data included in a file class for which 1 is set to SW_color and1 is set to SR_color. The seventh data is determined to be low inimportance as a file and thus, the writing management unit 20 arrangesthe seventh data in the MLC region.

If a write target memory region is determined by the above processing,the writing management unit 20 determines the physical address ofwriting destination. In this case, the writing management unit 20suppresses an occurrence of wear leveling to reduce unnecessary erasureprocessing by referencing the coloring table 14 to appropriately selectthe physical address of writing destination.

The wear leveling means interchanging (exchanging) data between blocksso that, for example, a difference between the maximum erasure count ofa block and the minimum erasure count of a block is within apredetermined threshold. For example, data in a NAND flash memory cannotbe overwritten without erasure processing and thus, a data movementdestination needs to be an unused block and erasure processing of ablock that has stored data arises.

Next, decision processing of the block into which data is to be writtenwill be described with reference to FIG. 20. FIG. 20 is a diagramillustrating decision processing of a write target block for data.

Data in the nonvolatile semiconductor memories 9, is erased in units ofblock. An erasure count EC for each block region of the nonvolatilesemiconductor memories 9, 10 can be acquired by referencing the memoryusage information 11. The ratio of the erasure count EC to the upperlimit of the erasure count (erasable upper limit count) of a blockregion is set as a wear-out rate.

If the erasure count EC of a block region reaches the erasable upperlimit count of the block region, the wear-out rate is 100%. If thewear-out rate is 100%, data is not written into the block region.

If the erasure count EC of a block region is close to the upper limit ofthe erasure count of the block region (for example, 90%), data writingfor the block region is decreased. The writing management unit 20 writeswrite target data whose writing frequency (the static writing frequencySW_color, the dynamic writing frequency DW_color) is low (for example,SW_color is 1 and DW_color is “medium”) into a block region with a highwear-out rate (for example, the wear-out rate is less than 90%) byreferencing the coloring table 14.

On the other hand, the erasure count EC of a block region is lower thanthe upper limit of the erasure count of the block region (for example,10%), numbers of data writing for the block region may be executed. Thewriting management unit 20 writes write target data whose writingfrequency (the static writing frequency SW_color, the dynamic writingfrequency DW_color) is high (for example, SW_color is 5 and DW_color is“high”) into a block region with a low wear-out rate (for example, thewear-out rate is less than 10%) by referencing the coloring table 14.

The block region into which the write target data is written isdetermined, as described above, based on coloring information of thewrite target data and the wear-out rate of the block region.Accordingly, the write target block region suited to properties (writingfrequency) of the write target data can be selected, improvingreliability of data. Moreover, as will be described below, the life of amixed main memory can be prolonged.

Next, details and effects of processing to determine the block regioninto which the write target data is written based on coloringinformation, the memory usage information 11, and the memory specificinformation 12 of the write target data with reference to FIGS. 21 to25.

FIG. 21 is a graph showing an example of a change of the erasure countin an arbitrary block of the nonvolatile semiconductor memories 9, 10.In FIG. 21, the vertical axis represents the erasure count and thehorizontal axis represents the time.

With the passage of time, an ideal erasure count of each block regionchanges. In the information processing device 1 using the nonvolatilesemiconductor memories 9, 10 such as a NAND flash memory, thenonvolatile semiconductor memories 9, 10 will deteriorate in the future,which makes replacement of the nonvolatile semiconductor memories 9, 10necessary. To use many block regions of the nonvolatile semiconductormemories 9, 10 before memory replacement, it is necessary to level outthe erasure count through wear leveling. FIG. 21 shows a change of theerasure count of an arbitrary block region of the nonvolatilesemiconductor memories 9, 10. It is preferable for the erasure count ofa block region to reach the erasable upper limit count when the lifeexpected of the block region is reached.

For example, in order for all block regions to follow the change of theerasure count shown in FIG. 21, the threshold for a difference of theerasure count of each block region can be set small for wear leveling.

FIG. 22 shows graphs showing an example of a change when the thresholdfor a difference of the erasure count is set small for wear leveling.

Broken lines in FIG. 22 show the range of a variation of the erasurecount of each block region. As shown in FIG. 22, the variation of theerasure count of each block region is made smaller by reducing thethreshold, but an occurrence count of erasure processing for wearleveling increases, which could result in a shorter life of the wholenonvolatile semiconductor memories 9, 10.

To reduce dispersion of the erasure count and suppress the occurrencecount of erasure processing by wear leveling, the writing managementunit 20 makes a selection of the erasure block region based on thememory usage information 11, the memory usage information 12, and thecoloring information 14 when data is written.

FIG. 23 is a graph showing an example of grouping of block regions inaccordance with the erasure count.

FIG. 24 is a diagram showing determination criteria for grouping blockregions in accordance with the erasure count.

In the present embodiment, each block region is grouped based on theerasure count. Information showing a result of grouping a block regionis stored as the memory usage information 11. Incidentally, theinformation showing the result of grouping the block region may also bestored as the memory specific information 12.

A thick line in FIG. 23 shows a change of a minimum erasure count and abroken line shows a threshold of wear leveling. As shown in FIG. 23,each block region is classified into a group of a respective erasurecount within a range of the threshold (within a range of a variation) ofwear leveling.

When one block region becomes writable again after data being erased,the memory usage information management unit 22 determines to whichgroup the block region belongs based on a determination table as shownin FIG. 24 and stores the group in the memory usage information 11.

In the determination table shown in FIG. 24, an interval between aminimum erasure count of erasure counts of all block regions and a valueobtained by adding the threshold for determining whether to implementwear leveling to the minimum erasure count is divided by the number ofgroups. The groups are set as h, g, f, e, d, c, b, a upward in thedivided range. In the determination table, the upper limit of theerasure count and the lower limit of the erasure count are set for eachgroup.

FIG. 25 is a diagram showing an example of a search of block regions forwear leveling.

The writing management unit 20 determines the group serving as areference to search for the block region of write target data based oninformation of the coloring table 14. If, for example, the accessfrequency of the write target data is high, a group whose erasure countis small is determined as the reference and if the access frequency ofthe write target data is low, a group whose erasure count is large isdetermined as the reference. It is assumed below that the group c isdetermined for the write target data.

When the group c is determined as a search reference for the writetarget data, as shown in FIG. 25, the writing management unit 20searches for a block region belonging to the determined group c of thewrite target data based on the memory usage information 11.

If a block region belonging to the determined group c of the writetarget data is present, the block region is determined as the writingdestination of the write target data.

On the other hand, if no block region belonging to the determined groupc of the write target data is present, the writing management unit 20searches for a block region belonging to the group b in the neighborhoodof the determined group c of the write target data.

If a block region belonging to the neighboring determined group b of thewrite target data is present, the block region belonging to theneighboring group b is selected as the writing destination of the writetarget data.

If no block region belonging to the neighboring determined group b ofthe write target data is present, a search of the neighboring group d ofthe group c for the write target data is further performed similarlyuntil the block region is determined. When a physical address of theblock region into which the data is written is determined by the searchprocessing, the writing management unit 20 writes the data and theaddress management unit 18 updates the address conversion information13.

Incidentally, the writing management unit 20 may determine an address ofthe writing destination by using another search method of a blockregion. For example, the writing management unit 20 manages writableblock regions (erasure processed) as a tree structure (such as B−Tree,B+Tree, RB−Tree, or the like) in which the erasure count is used as akey and an erasure block region is used as a node and stores the treestructure in the memory specific information 12 or the memory usageinformation 11. The writing management unit 20 searches the tree byusing a reference erasure count as a key to extract a block region withthe closest erasure count.

When data is erased by the arbitrary process 3 b, the operating system27 erases content of the coloring table 14 about the data. When contentof the coloring table 14 is erased, the address management unit 18erases a physical address corresponding to a logical address of theerased data in the address conversion information 13.

If data is present in the volatile semiconductor memory 8, the data inthe volatile semiconductor memory 8 is erased.

Next, a configuration including a cache memory in the memory managementdevice 1 according to the present embodiment will be described withreference to FIG. 26. FIG. 26 is a block diagram showing an example ofthe memory management device further including a cache memory in thememory management device 1 according to the present embodiment. In FIG.26, the processor 3 b of the processors 3 a, 3 b, 3 c willrepresentatively be described, but the other processors 3 a, 3 c canalso be described in the same manner.

The memory management device 1 further includes a cache memory 28.

The processor 3 b can directly access the primary cache memory 4 b thesecondary cache memory 5 b, and further the cache memory 28.

When page-in or page-out occurs in one of the primary cache memory 4 b,the secondary cache memory 5 b, and the cache memory 28, the memorymanagement device 28 accesses the mixed main memory 2.

An implementation example of the memory management device 1, the mixedmain memory 2, and the processor 3 will be described based on an examplein FIG. 27.

FIG. 27A is a block diagram showing a first implementation example ofthe memory management device 1, the mixed main memory 2, and theprocessor 3 a. In FIG. 27A, a case when the volatile semiconductormemory 8 is a DRAM and the nonvolatile semiconductor memories 9, 10 areNAND flash memories will be described, but the present embodiment is notlimited to such an example.

The processor 3 a includes a memory controller (MMU) 3 ma, the primarycache memory 4 a, ands the secondary cache memory 4 b. The memorymanagement device 1 includes a DRAM controller. The processor 3 a andthe memory management device 1 are formed on the same board (forexample, SoC).

The volatile semiconductor memory 8 is controlled by the DRAM controllerincluded in the memory management device 1. The nonvolatilesemiconductor memories 9, 10 are controlled by the memory managementdevice 1. In the implementation example in FIG. 27A, the memory moduleon which the volatile semiconductor memory 8 is mounted and the memorymodule on which the nonvolatile semiconductor memories 9, 10 are mountedare separate modules.

FIG. 27B is a block diagram showing a first implementation example ofthe memory management device 1, the mixed main memory 2, and theprocessor 3 a. In FIG. 27B, a case when the volatile semiconductormemory 8 is a DRAM and the nonvolatile semiconductor memories 9, 10 areNAND flash memories will be described, but the present embodiment is notlimited to such an example. The description of the same elements asthose in FIG. 27A is omitted.

In the example of FIG. 27B, the memory management device 1 iselectrically connected to the chip on which the processor 3 a is mountedfrom outside. Also, the volatile semiconductor memory 8 is connected tothe memory management device 1. The memory management device 1 includesthe DRAM controller (not shown).

Next, another configuration mode of the memory management device 1 andthe information processing device 100 according to the presentembodiment will be described with reference to FIG. 28. In the memorymanagement device 1 and the information processing device 100 shown inFIG. 1, counting (incrementing) for the writing count DWC_color and thereading count RWC_color of data are managed by the dynamic colorinformation management unit 22 of the memory management device 1. In thememory management device 1 and the information processing device 100shown in FIG. 28, by contrast, the writing count DWC_color and thereading count RWC_color of data are counted by memory controllers 3 ma,3 mb, 3 mc included in the processors 3 a, 3 b, 3 c. In the descriptionthat follows, the memory controller 3 ma of the memory controllers 3 ma,3 mb, 3 mc will representatively be described, but the other memorycontrollers 3 mb, 3 mc are also described in the same manner.

The memory controller 3 ma included in the processor 3 a includes acounter cta that counts the writing count DWC_color and the readingcount DRC_color of data. Further, the memory controller 3 ma includescount information cia that manages the writing count DWC_color and thereading count DRC_color of data.

When, for example, the processor 3 a causes a load instruction on data,the counter cta counts (increments) the reading count DRC_color of thedata and updates the count information cia. Also when, for example, theprocessor 3 a causes a store instruction on data, the counter cta counts(increments) the writing count DWC_color of the data and updates thecount information cia.

The writing count DWC_color and the reading count DRC_color of datamanaged by the count information cia are periodically reflected in thewriting count DWC_color and the reading count DRC_color of the coloringtable 14 of the memory management device 1 of the data.

In the configuration mode in FIG. 28, the following effect is gained.That is, if the operating frequency of the memory management device 1 ison the order of MHz while the operating frequency of the processor 3 ais on the order of GHz, a case when it is difficult for the memorymanagement device 1 to count writing and reading caused by the processor3 a can be considered. In the configuration mode in FIG. 28, bycontrast, writing and reading are counted by the counter cta of theprocessor 3 a and thus, the writing count and reading count at highoperating frequency can be counted.

Next, a configuration in which a plurality of nonvolatile semiconductormemories is managed by a plurality of the memory management devices 1will be described with reference to FIG. 29. FIG. 29 is a perspectiveview showing an example of the plurality of memory management devicesmanaging the plurality of nonvolatile semiconductor memories.

In FIG. 29, one memory module 30 is formed from the one memorymanagement device 1 and a plurality of NAND flash memories 29. In theexample of FIG. 29, the three memory modules 30 are formed.

The plurality of nonvolatile semiconductor memories 29 is, for example,a NAND flash memory and is used as the nonvolatile semiconductormemories 9, 10 described above.

The memory management device 1 manages access to the plurality ofnonvolatile semiconductor memories 29 belonging to the same memorymodule 30.

Further, the plurality of the memory management devices 1 included in aplurality of the memory modules 30 operates like one memory managementdevice in cooperation with each other.

The memory management device 1 of the memory module 30 includes an ECCfunction and a RAID function for the plurality of nonvolatilesemiconductor memories 29 in the memory module 30 and performs mirroringand striping.

Even when the memory module 30 is conducting (operating), each of thenonvolatile semiconductor memories 29 can be hot-swapped (exchanged). Abutton 31 is associated with each of the plurality of nonvolatilesemiconductor memories 29.

The button 31 includes a warning output unit (for example, an LED). If,for example, the warning output unit is in a first color (green), thenormal state is indicated and if the warning output unit is in a secondcolor (red), a state requiring swapping is indicated.

If the button 31 is pressed, a notification is sent to the processes 6a, 6 b, 6 c and the operating system 27 and if it is safe to dismountsuch as when no access occurs, the button 31 turns to a third color(blue) and the nonvolatile semiconductor memory 29 corresponding to thebutton 31 becomes hot-swappable.

In executing hot-swapping, a lamp indicating that the nonvolatilesemiconductor memory 29 is hot-swappable is lit when write-back iscompleted after the button 31 requesting hot-swapping being pressed andthen, the nonvolatile semiconductor memory 29 is swapped.

The processing unit 15 of the memory management device 1 determineswhether or not the writing count or reading count of each of thenonvolatile semiconductor memories 29 has reached a predetermined ratioof the accessible upper limit count written in the memory specificinformation 12 by referencing the memory usage information 11 and thememory specific information 12 stored in the information storage unit17. If the writing count or reading count is reached the predeterminedratio of the writable upper limit count or readable upper limit count,the processing unit 15 issues a notification or warning of memoryswapping.

In the present embodiment, if the page size or block size of thenonvolatile semiconductor memories 29 is large, pre-loading iseffective.

If pre-loading is implemented, the processing unit 15 of the memorymanagement device 1 pre-loads data likely to be accessed frequently inthe cache memory 28 in advance by referencing coloring informationcorresponding to data stored in the nonvolatile semiconductor memories29.

Alternatively, the processing unit 15 pre-loads periodic data that islikely to be accessed in a predetermined time prior to the predeterminedtime.

In the present embodiment, the arrangement of data is determined basedon durability of each memory in the mixed main memory 2 so that the lifeof the mixed main memory 2 can be prolonged. Moreover, fast access tothe mixed main memory 2 can be realized.

Because data is arranged based on durability of each memory in the mixedmain memory 2 in the present embodiment, fatal data losses in the mixedmain memory 2 can be prevented.

Swapping can be eliminated by using the memory management device 1 andthe mixed main memory 2 according to the present embodiment.

In the present embodiment, the nonvolatile semiconductor memories 9, 10are used as a main memory. Accordingly, the storage capacity of the mainmemory can be increased and a second storage device using a hard disk orSSD (Solid State Disk) does not have to be used.

Because the nonvolatile semiconductor memories 9, 10 are used as a mainmemory in the present embodiment, instant-on can be made faster.

Second Embodiment

The basic type of computer architecture, the Neumann architecture, has aproblem called the von Neumann bottleneck caused by a difference betweenthe CPU's frequency and main memory's speed. When a volatile memory isused as the main memory, this problem has been mitigated by installing ahigh-speed cache memory (such as an SRAM) between the main memory andCPU core.

Recently, a technology to use a nonvolatile semiconductor memory slowerthan a volatile semiconductor memory as the main memory has beendeveloped. In this case, the above problem manifests itself moremarkedly. Thus, it is necessary to improve the hit rate of the cachememory.

In the present embodiment, a memory management device capable ofimproving the hit rate of the cache memory when a nonvolatilesemiconductor memory is used as the main memory will be described.

The present embodiment uses the nonvolatile semiconductor memories 9, 10as the main memory and a portion of the volatile semiconductor memory 8as the cache memory. In the present embodiment, the volatilesemiconductor memory 8 used as the cache memory will be described.

FIG. 30 shows a physical address space of the volatile semiconductormemory (hereinafter, simply called the cache memory) 8.

In the present embodiment, the physical address space of the cachememory 8 is divided into a plurality of areas (L0 to L5). Each area doesnot have to be contiguous in the physical address space. The size ofeach area is set in such a way that, for example, the physical addressspace increases from lower to upper areas. Further, an upper area isenabled to expand the area thereof to the adjacent lower area. Themaximum expansion size of each area is managed by an area limit ELM.

An upper area has a larger area size and thus, data in the area islikely to be held for a long period of time. On the other hand, a lowerarea is a smaller area size and thus, data in the area is likely to beheld for only a short period of time.

In the present embodiment, data whose write out priority is low isarranged in an upper area and data whose write out priority is high isarranged in a lower area. The arrangement processing is performed by,for example, the writing management unit 20 in FIG. 1. The write outpriority is determined by using coloring information. “Write out” meansmovement of data from the volatile semiconductor memory 8 to thenonvolatile semiconductor memories 9, 10.

The cache memory 8 includes a cache header CHD. The cache header CHDstores management information of each area. That is, the area limit ELM,a free cache line list FCL, and an area cache line list ECL of each areaare stored in the cache header CHD.

The free cache line list FCL is a data structure that manages free spaceof the cache memory 8 and stores a plurality of nodes as managementinformation corresponding to cache lines belonging to no area.

The area cache line list ECL is a data structure that manages used spaceof the cache memory 8 and stores nodes acquired from the free cache linelist FCL for each area.

A content of the cache header CHD is initialized by reading from anonvolatile semiconductor memory when the information processing device100 is activated. When the information processing device 100 isterminated, the content of the cache header CHD is saved in thenonvolatile semiconductor memory.

When the information processing device 100 is activated (when coldboot), a content set by the operation system is recorded in the cacheheader CHD to generate basic information of each area.

Incidentally, the area limit ELM can be set by the user to fit to theusage form of the user and an interface to enable the setting may beprovided.

Details of the free cache line list FCL, the area cache line list ECL,and the node will be described later.

Data written into the mixed main memory 2 includes, as described above,coloring information as hint information to determine an arrangement(writing) region in the mixed main memory 2. Thus, by controlling datawriting into each area of the cache memory 8 by using the coloringinformation, the hit rate of the cache can be improved. Accordingly, thefrequency with which data is read to the nonvolatile semiconductormemories 9, 10 can be reduced so that the nonvolatile semiconductormemories 9, 10 can be protected.

FIGS. 31A and 31B and FIGS. 32A and 32B show examples of tables (CET)showing a correspondence relationship between coloring information ofthe coloring table 14 and each area of the cache memory 8 shown in FIG.30.

FIG. 31A gives a higher priority to read access to enable improvement ofthe hit rate of reading. More specifically, FIG. 31A shows thecorrespondence relationship among the data life SL_color as coloringinformation, the static reading frequency information SR_color, and thedynamic reading frequency DR_color, and the area of the volatilesemiconductor memory 8. As shown in FIG. 31A, data having an increasingreading frequency with an increasing value of the static readingfrequency information SR_color is arranged in an increasingly upper areaof the volatile semiconductor memory 8. That is, to give a higherpriority to read access, the static reading frequency informationSR_color and the dynamic reading frequency DR_color are referenced toarrange the static reading frequency information SR_color and thedynamic reading frequency DW_color in an upper area with a larger areasize. The upper area has a larger area size and data in the area islikely to be held for a long period of time. Thus, the cache hit rate ofread access can be improved.

Data whose data life is “S” is arranged in area L5 regardless of othercoloring information. For example, data in the process of operation hasa short data life and the need for writing the data into the nonvolatilesemiconductor memories 9, 10 is low. However, a large number of piecesof such data exist. Thus, such data is arranged in area L5 with thelargest size in the cache memory 8.

FIG. 31B gives a higher priority to write access to enable improvementof the hit rate of writing. More specifically, FIG. 31B shows thecorrespondence relationship among the data life SR_color as coloringinformation, the static writing frequency information SR_color, and thedynamic writing frequency information DW_color, and the area of thevolatile semiconductor memory 8. That is, to give a higher priority towrite access, the static writing frequency information SW_color and thedynamic writing frequency information DW_color are referenced to arrangethe static writing frequency information SR_color and the dynamicwriting frequency SW_color in an upper area with a larger area size.Accordingly, the cache hit rate of write access can be improved.

Data whose data life is “S” is arranged, like in FIG. 31A, in area L5.

FIG. 32A takes both of the reading frequency and the writing frequencyinto consideration and improvement of the hit rate is enabled if atleast one of the reading frequency and the writing frequency is high.More specifically, FIG. 32A shows the correspondence relationship amongthe data life SL_color as coloring information, the sum of the value ofthe static reading frequency information SR_color and the value of thestatic writing frequency information SW_color, and the area of thevolatile semiconductor memory 8.

FIG. 32B is a modification of FIG. 32A, the reading frequency andwriting frequency are weighted, and enables improvement of the hit rateby setting weights to the reading frequency and writing frequency. Incontrast to FIG. 32A, the area of the volatile semiconductor memory 8 isassociated with the value of SR_color*W+SW_color*(1−W).

In FIGS. 32A and 32B, data whose data life is “S” is arranged, like inFIGS. 31A and 31B, in area L5.

One of the tables CET showing relationships between coloring informationand areas shown in FIGS. 31A and 31B and FIGS. 32A and 32B is stored in,for example, the information storage unit 17.

Relationships between coloring information and areas are not limited toexamples shown in FIGS. 31A and 31B and FIGS. 32A and 32B and can bechanged in response to a user's request. Thus, areas of the volatilesemiconductor memory 8 are set to be expandable to have expandability.

Next, an example of a management method of a cache area will bedescribed with reference to FIG. 33. FIG. 33 shows an example of thefree cache line list FCL and the area cache line list ECL stored in thecache header CHD of the cache memory 8.

The free cache line list FCL is, as described above, a data structureshowing a free space of the cache memory 8 and is composed of aplurality of nodes ND corresponding to cache lines. Each node ND iscomposed of a physical address of a cache line, a belonging area, and anupdate flag.

The cache line corresponds to the page size (I/O size) of thenonvolatile semiconductor memories 9, 10. Each node ND stores thephysical address of a cache line.

The belonging area is one of areas L0 to L5 set to the cache memory.

The update flag is a flag indicating whether or not an update of data ofthe cache line has occurred. “0” of the update flag indicates that datahas been erased or data has been written into the volatile semiconductormemory 8 and the written data has not been updated.

“1” of the update flag indicates that data in a cache line has beenupdated and the update of the data has not been reflected in thenonvolatile semiconductor memories 9, 10.

The update flag is controlled by, for example, the processing unit 15.The processing unit 15 sets the corresponding update flag to “0” whendata is written from the nonvolatile semiconductor memories 9, 10 intothe cache memory 8 and sets the update flag to “1” when the written datais updated in the cache memory 8. The processing unit 15 also sets thecorresponding update flag to “0” when data in the cache memory 8 iserased and further sets the corresponding update flag to “0” when anupdate of data of the cache memory 8 is reflected in the nonvolatilesemiconductor memories 9, 10.

Incidentally, the update flag may not be arranged in each node and, forexample, a content of a field indicating a dirty bit stored in theinformation storage unit 17 may be referenced.

On the other hand, the area cache line list ECL is, as described above,a data structure that manages a used space of the cache memory 8 andstores the node corresponding to the cache line contained in each area.That is, when data read from the nonvolatile semiconductor memories 9,10 is written into the cache memory 8, a belonging area of each node ofthe free cache line list FCL is searched based on coloring informationattached to the data and if free space is available, the node thereof isacquired and arranged in the corresponding area of the area cache linelist ECL. If write data is data to be written into area L5, each node ofthe free cache line list FCL is searched and one node of area L5 orlower areas L4 to L0 as an expansion region is acquired. The acquirednode is connected to the area cache line list ECL corresponding to areaL5.

The data is also written into the cache memory 8 according to thephysical address of the cache line of the acquired node. Further, theupdate flag of the node ND is set to “0”.

The area cache line list ECL is managed based on an algorithm such asFIFO (First-in/First-out) and LRU (Least Recently Used). Thus, if, forexample, nodes are acquired from the free cache line list FCLcorresponding to each area, the acquired nodes are sorted based on a setalgorithm.

The cache line corresponding to the node positioned, for example, at thehead of the area cache line list ECL is always a write out target of thearea.

The number of nodes arranged corresponding to each area in the areacache line list ECL is managed by the area limit ELM so that the lengthof the list of each area should not exceed the area limit ELM.

In FIG. 33, the management by software processing using the cache headeris described as the management method of the cache area, but amanagement by hardware using a configuration in which the cache line ismanaged by a cache tag may also be used.

FIG. 34 shows write processing of data by, for example, the processingunit 15. That is, FIG. 34 shows a flow of processing when data is newlyread from the nonvolatile semiconductor memories 9, 10 and anarrangement of the data in the volatile semiconductor memory 8 isdetermined. The size of each area is variable in the present embodimentand thus, the process until data is written changes depending on whetheror not an area is expandable.

In FIG. 34, when data is to be arranged in the cache memory 8, first adata arrangement area of the cache memory 8 is determined (step S31).That is, an area of the cache memory 8 to arrange the read data isdetermined based on the correspondence relationships shown in FIGS. 31Aand 31B and FIGS. 32A and 32B.

More specifically, for example, the table CET shown in FIG. 31A isreferenced based on coloring information attached to data read from thenonvolatile semiconductor memories 9, 10. If the data life of thecoloring information attached to data is “L”, the value of the staticreading frequency information SR_color is “1”, and the reading frequencyis “high”, the data is arranged in the area L0. If the data life of thecoloring information attached to data is “L”, the value of SR_color is“4”, and the reading frequency is “high”, the data is arranged in thearea L4.

Next, whether or not the area is expandable is determined (step S32).The current size of the area can be recognized from, for example, thenumber of nodes of the area cache line list. Thus, the current sizecompares with the value of the area limit ELM written in the cacheheader CHD. If, as a result, the current size is smaller than the valueof the area limit ELM, the area is determined to be expandable.

If the area is expandable, whether or not the node ND corresponding tothe area is present in the free cache line list FCL is determined (stepS33). That is, belonging areas of nodes in the free cache line list FCLare searched to determine whether the corresponding area is present. Inthis case, if data is data to be written into the area L4, the area L4is expandable to a portion of the area L3 and thus, the area L4 and areaL3 are searched.

If, as a result, the corresponding node ND is present, the node ND isacquired from the free cache line list (step S34).

The physical address of the cache line is acquired from the acquirednode ND. Based on the physical address, the data read from thenonvolatile semiconductor memories 9, 10 is written into the cachememory 8 (step S35).

Then, the cache header CHD is updated (step S36). That is, the node NDacquired from the free cache line list FCL is moved to the area cacheline list ECL and the update flag is set to “0”.

Next, the address conversion table is updated (step S37). That is, thephysical address of the nonvolatile semiconductor memories 9, 10corresponding to the data written into the cache memory 8 is writteninto the address conversion table.

On the other hand, if, in step S33, the corresponding node ND isdetermined not to be present in the free cache line list FCL, the areacache line list ECL is searched from the bottom area (step S38). Thatis, to generate the new node ND, it is necessary to transfer any onepiece of data in the cache memory 8 to the nonvolatile semiconductormemories 9, 10 to generate a free area. Thus, all areas from the bottomarea L0 to area L5 of the area cache line list ECL shown in FIG. 33 aresearched.

If, for example, data read from the nonvolatile semiconductor memories9, 10 is data to be written into the area L4, the area L4 is expandableto a portion of the lower area. Thus, the node ND of the lower area ofthe area cache line list ECL is acquired.

Next, whether the node ND has been acquired is determined (step S39).When, as a result, the node ND is acquired, the physical address of thecache line is acquired from the acquired node ND and the data in thecache memory 8 is written into the nonvolatile semiconductor memories 9,10 based on the physical address (step S40).

Then, the cache header CHD is updated (step S41). That is, the free nodeND is generated by the data corresponding to the node ND of the areacache line list ECL being written into the nonvolatile semiconductormemories 9, 10. The node ND is moved to the free cache line list FCL andthe update flag is set to data “0”.

Next, the control is moved to step S33. In this case, the free node NDis present in the free cache line list FCL and thus, the node ND isacquired and the data is written to the physical address specified bythe node (steps S33 to S35). Next, the cache header CHD and the addressconversion table are updated (steps S36 and S37).

If, in step S32, the area expansion is determined to be difficult, thenodes ND of the area in the area cache line list ECL are searched andthe first node ND is acquired (step S42). The acquired node ND is a nodeof an area whose priority is low.

Then, like the operation described above, the physical address of thecache line is acquired from the acquired node, and the data in the cachememory 8 is written into the nonvolatile semiconductor memories 9, basedon the physical address (step S40). Then, the cache header is updated(step S41).

Further, if, in the step S39, the node ND cannot be acquired as a resultof searching the area cache line list ECL, the cache memory 8 cannot beused and thus, the data is written into the nonvolatile semiconductormemories 9, 10 (step S43). Then, the address conversion table is updated(step S37). (Erasure of the cache memory)

FIG. 35 shows an example of an erasure operation of the cache memory 8.The cache memory 8 is assumed to be erasable by software.

If, as shown in FIG. 35, an erasure request of data stored in the cachememory 8 is issued (step S51), update flags of each node ND are searchedto detect data not yet updated to the nonvolatile semiconductor memories9, 10 (step S52). That is, for example, a node whose update flag is data“1” in the area cache line list ECL is detected. As a result, if thereis no update flag with the data “1”, the processing ends.

If an update flag with the data “1” is detected, the data in the cachememory 8 is written into the nonvolatile semiconductor memories 9, 10based on the physical address of the cache line of the node ND (stepS53).

Then, the cache header CHD is updated (step S54). That is, the node ofthe area cache line list ECL is moved to the free cache line list FCLand the update flag is set to data “0”. Next, the control is moved tostep S52. Such an operation is repeated until there is no longer anupdate flag with the data “1”.

According to the second embodiment, data whose importance is high isstored in an upper area of the volatile semiconductor memory 8 based onthe relationship between coloring information attached to data and areasof the cache memory 8. Therefore, the hit rate of the cache memory 8 canbe improved.

Because the hit rate of the cache memory 8 is high, the number of timesof accessing the nonvolatile semiconductor memories 9, 10 can be reducedso that the nonvolatile semiconductor memories 9, 10 can be protected.

Moreover, upper areas have an expansion region and data can be writtenthereinto until the expansion region is full. If the area is small, datawhose importance is high but is not accessed frequently is likely to bewritten back from the cache memory 8 based on, for example, an algorithmof LRU. However, data infrequently accessed can be left in the cachememory by making an upper area expandable to lower areas to secure awide area including the expansion region. Therefore, the hit rate of thecache memory 8 can be improved.

The cache memory 8 is divided into the areas of L0 to L5 for each pieceof coloring information. When, for example, the area L5 as an upper areastores data equal to or more than a specified size, the area can beexpanded to a portion of the area L4 thereunder. If data is written intoan expansion region and the area cannot be further expanded, data in thecache memory 8 is written back to the nonvolatile semiconductor memories9, 10 based on an algorithm such as FIFO, LRU, or the like. The bottomarea L0 has no expansion region and if the area becomes full, data inthe cache memory 8 is written back based on an algorithm such as FIFO,LRU, or the like. Thus, data whose writing frequency is high can bestored in the cache memory for a long period of time. Therefore, thenonvolatile semiconductor memories 9, 10 whose erasure count is limitedcan be protected.

Third Embodiment

Next, the memory management device according to the third embodiment andthe control method thereof will be described with reference to FIGS. 36to 42. The present embodiment is a modification of the first embodiment.The present embodiment relates to an example capable of reducing thenumber of times of accessing the nonvolatile semiconductor memories(NAND flash memories) 9, 10 so that the memory life can be prolonged. Inthe description, a detailed description overlapping with the descriptionin the first embodiment is omitted.

<Truth Value of the Valid/Invalid Flag of Address ConversionInformation>

First, the truth value of the valid/invalid flag indicatingpresence/absence of data in the nonvolatile semiconductor memories 9, 10held by the address conversion information 13 in FIG. 4 will bedescribed using FIG. 36.

As illustrated in FIG. 36, the initial value of the flag is “0”.

The flag “0(invalid)” indicates that the corresponding logical addressis not mapped to the nonvolatile semiconductor memories 9, 10 or hasbeen erased after being mapped.

The flag “1(valid)” indicates that the corresponding logical address ismapped to at least one of the nonvolatile semiconductor memories 9, 10.

The flag “0(invalid)” indicates that when all pages in a block in thenonvolatile semiconductor memories 9, 10 has the flag “0(invalid)”, alldata in the block can be erased. Even a page having the flag “0(valid)”makes the block non-erasable.

<State Transition of the Valid/Invalid Flag>

Next, a state transition of the valid/invalid flag of the nonvolatilesemiconductor memories 9, 10 will be described using FIG. 37.

As illustrated, when mapped to the nonvolatile semiconductor memories 9,10, the valid/invalid flag makes a state transition from the flag “0” to“1”. On the other hand, when data in the nonvolatile semiconductormemories 9, 10 is to be erased, the valid/invalid flag makes a statetransition from the flag “1” to “0”.

<1. Processing Flow of a Memory Release Request>

Next, the processing flow of a memory release request of the mixed mainmemory 2 will be described along FIG. 38.

(S001)

As illustrated, in step S001, for example, an operating system OS(corresponding to the operating system 27 in the first embodiment) ofthe processor 3 a sends a memory release request (argument: logicaladdress) of the volatile semiconductor memory 8 to the memory managementdevice 1.

(S002)

Subsequently, in step S002, the memory management device 1 that hasreceived the memory release request references the address conversioninformation (address conversion table) 13 to examine whether a physicaladdress in the volatile semiconductor memory 8 corresponding to thelogical address as the argument of the memory release request has avalue that is not undefined and also the valid/invalid bit of thenonvolatile semiconductor memories 9, 10 to check whether or not anapplicable data is in the volatile semiconductor memory 8 or thenonvolatile semiconductor memories 9, 10.

That is, if the valid/invalid bit of the nonvolatile semiconductormemories 9, 10 in the address conversion information 13 is “0”, thememory management device 1 determines that the logical address as theargument is not mapped to the nonvolatile semiconductor memories 9, 10and if the valid/invalid bit of the nonvolatile semiconductor memories9, 10 is “1”, the memory management device 1 determines that the logicaladdress as the argument is mapped to the nonvolatile semiconductormemories 9, 10.

Then, if the valid/invalid bit of the nonvolatile semiconductor memories9, 10 is “1”, the memory management device 1 references the physicaladdress of the volatile semiconductor memory 8 and the physicaladdresses of the nonvolatile semiconductor memories 9, to checkpresence/absence of the data in the volatile semiconductor memory 8 andthe nonvolatile semiconductor memories 9, 10 and exercises the followingcontrol:

Case 1 (the data is present in the DRAM 8 and the NAND 9, 10)

(S003)

Subsequently, in step S003, if the data is present in the volatilesemiconductor memory 8 and the nonvolatile semiconductor memories 9, 10,the memory management device 1 erases data at the physical address inthe volatile semiconductor memory 8 corresponding to the logical addressrequested to release to form explicit free space in the volatilesemiconductor memory 8 and sets a dirty bit of the volatilesemiconductor memory 8 to “0”. The dirty bit of the volatilesemiconductor memory 8 is a bit indicating that data in the volatilesemiconductor memory 8 has been rewritten and is present, for example,in a header region or the like of the volatile semiconductor memory 8.

(S004)

Subsequently, in step S004, the memory management device 1 sets avalid/invalid bit of a physical address in the nonvolatile semiconductormemories 9, 10 corresponding to a logical address requested to releaseto “0” for invalidation as an erasure target, for the nonvolatilesemiconductor memories 9, 10. At this point, a data erasure operationactually is not performed on the nonvolatile semiconductor memories(NAND) 9, 10 in a strict sense and only the valid bit is removed as anerasure target.

Case 2 (the data is present only in the DRAM 8)

(S005)

Subsequently, in step S005, if the data is present only in the volatilesemiconductor memory 8, the memory management device 1 similarly erasesdata at the physical address in the volatile semiconductor memory 8corresponding to the logical address requested to release to formexplicit free space and sets a dirty bit of the volatile semiconductormemory 8 to “0”.

In the present example, there is no need to consider a case when thespecified data is present only in the nonvolatile semiconductor memories(NAND) 9, 10 (the data is not cached) because the reduction of thenumber of times of accessing the nonvolatile semiconductor memories(NAND) 9, 10 is intended by forming free space in the volatilesemiconductor memory (DRAM) 8. If the data corresponding to the logicaladdress requested to release is not present in the volatilesemiconductor memory 8 and is present only in the nonvolatilesemiconductor memories 9, 10, it is only necessary to set thevalid/invalid flag to “0” (invalidate).

<1-2. Explicit Space Region in the Volatile Semiconductor Memory 8 by aMemory Release Request>

As described above, the memory management device 1 according to thepresent example receives a logical address specifying a release positionfor the mixed main memory 2 including the volatile semiconductor memory(first memory) 8 and the nonvolatile semiconductor memories (secondmemory) 9, 10 from the processor 3 and examines the specified logicaladdress, the physical address of the volatile semiconductor memory(first memory) 8, the physical addresses of the nonvolatilesemiconductor memories (second memory) 9, 10, and the valid/invalid flagof data at a physical address of the nonvolatile semiconductor memories(second memory) 9, 10 by referencing the address conversion information13 to check the physical address at which data corresponding to thelogical address requested to release is present. Then, if thecorresponding data is present in the volatile semiconductor memory(first memory) 8, the memory management device 1 erases the data to formexplicit free space and if the corresponding data is also present in thenonvolatile semiconductor memories (second memory) 9, 10, the memorymanagement device 1 does not actually perform an erasure operation ofthe data, but invalidates the valid/invalid flag by setting the flag to“0”. In other words, the memory management device 1 forms explicit freespace in the volatile semiconductor memory (DRAM) 8 for the logicaladdress specified by the memory release request.

FIG. 39 is a diagram illustrating a formation of explicit free space inthe volatile semiconductor memory when a release of a memory in FIG. 38is requested. For example, as illustrated, erased explicit free spaceFSO can be formed at a physical address xh corresponding to the logicaladdress specified by a memory release request in memory space of thevolatile semiconductor memory (DRAM) 8.

Accordingly, the amount of data of the volatile semiconductor memory 8can be reduced and thus, the number of times of accessing thenonvolatile semiconductor memories 9, 10 can advantageously be reducedto prolong the memory life of the nonvolatile semiconductor memories 9,10.

<2. Processing Flow of a Memory Acquisition Request>

Next, the processing flow of a memory acquisition request of the mixedmain memory 2 will be described along FIG. 40.

(S011)

As illustrated, in step S011, for example, an application App in theprocessor 3 a sends a memory acquisition request to the operating systemOS.

(S012)

Subsequently, in step S012, the operating system OS secures a portion ofa free (any) logical address. In this stage, the secured logical addressis not yet mapped to a physical address in the volatile semiconductormemory or the nonvolatile semiconductor memory and will be mapped onlywhen a writing request is received. In the present example, a memoryregion can be secured based on coloring information (hint information)before data reading and data writing described below. Thus, the presentexample is advantageous in that the memory life of the nonvolatilesemiconductor memories 9, 10 can be prolonged.

(S013 (Data Reading Request))

Subsequently, in step S013, the application App requests data readingfor the operating system OS.

(S014)

Subsequently, in step S014, the operating system OS requests datareading for the memory management device 1.

Then, the memory management device 1 searches for an entry correspondingto the logical address for which a data reading request is made byreferencing the address conversion information 13.

If mapped, data at the physical address in the volatile semiconductormemory 8 or the nonvolatile semiconductor memories 9, 10 correspondingto the logical address for which a data reading request is made isreturned. On the other hand, if not yet mapped and an undefined value isat the physical address, data cleared to zero is instead returned.

Details thereof will be described later along the flow in FIG. 41.

(S015 (Data Writing Request))

Subsequently, in step S015, the application App requests data writingfor the operating system OS.

(S016)

Subsequently, in step S016, the operating system OS requests datawriting for the memory management device 1.

Then, the memory management device 1 references the address conversioninformation 13 to enter a mapping result for the secured logical address(the physical address in the volatile semiconductor memory or thenonvolatile semiconductor memory). If mapped to the nonvolatilesemiconductor memories 9, 10, the valid/invalid flag indicatingpresence/absence of data in the nonvolatile semiconductor memories 9, 10is validated by setting the flag to “1”.

Details thereof will be described later along the flow in FIG. 42.

<2-1. Processing Flow when a Memory Data Read is Requested>

The processing flow of a memory data reading request in step S014 willbe described in detail along FIG. 41.

(S201)

As illustrated, in step S201, for example, the application App of theprocessor 3 a first requests reading for the operating system OS and theoperating system OS requests a memory data reading for the memorymanagement device 1 by specifying the logical address.

(S202)

Subsequently, in step S202, the memory management device 1 that isreceived a memory data reading request determines whether datacorresponding to the logical address is present in the volatilesemiconductor memory 8 by referencing the address conversion information(table) 13.

(S203)

Subsequently, in step S203, if a determination is made in step S202 thatdata corresponding to the logical address is present in the volatilesemiconductor memory 8 (Yes), the operating system OS reads the data atthe physical address in the volatile semiconductor memory 8corresponding to the logical address by the memory management device 1and terminates the operation (End).

(S204)

Subsequently, in step S204, if a determination is made in step S202 thatdata corresponding to the logical address is not present in the volatilesemiconductor memory 8 (No), the memory management device 1 determineswhether data corresponding to the logical address is present in thenonvolatile semiconductor memories 9, 10 by referencing the addressconversion information (table) 13 again.

(S205)

Subsequently, in step S205, if a determination is made in step S204 thatcorresponding data is present in the nonvolatile semiconductor memories9, 10 (Yes), the operating system OS reads the data stored in thenonvolatile semiconductor memories 9, 10 corresponding to the logicaladdress by the memory management device 1.

(S206)

Subsequently, in step S206, the operating system OS writes the data readfrom the nonvolatile semiconductor memories 9, 10 in step S205 into thevolatile semiconductor memory 8 by the memory management device 1.

(S207)

Subsequently, in step S207, the memory management device 1 sets thephysical address in the volatile semiconductor memory 8 of an entry ofthe address conversion information 13, sets the valid/invalid bit in theaddress conversion information 13 to “1”, sets a dirty bit to “0”, andterminates the operation (End).

(S208)

Subsequently, in step S208, if a determination is made in step S204 thata corresponding address is not present in the nonvolatile semiconductormemories 9, 10 (No), the operating system OS sends zero-cleared datacreated by the memory management device 1 to the processor 3 a side,terminates the operation (End).

“Sending zero-cleared data to the processor 3 a side” essentially meansthat if the data is actually present in at least one of the volatilesemiconductor memory and nonvolatile semiconductor memories, a contentof the data present at the physical address corresponding to the logicaladdress is sent. In this case, however, the data is not yet mapped andthere is no corresponding data and thus, instead of actually sending thecontent of the data, data padded with zeros for the size is sent asdata.

Thereafter, the zero-cleared data may be written into the volatilesemiconductor memory 8.

<2-2. Processing Flow when a Memory Data Writing is Requested>

The processing flow when a memory data writing is requested in step S016will be described in detail along FIG. 42.

(S301)

As illustrated in FIG. 42, in step S301, for example, the applicationApp of the processor 3 a first requests writing request for theoperating system OS and the operating system OS requests memory datawriting for the memory management device 1 by specifying the logicaladdress.

(S302)

Subsequently, in step S302, the memory management device 1 that receivesa memory data writing request determines whether data corresponding tothe logical address is present in the volatile semiconductor memory 8 byreferencing the address conversion information (table) 13.

(S303)

Subsequently, in step S303, if a determination is made in step S302 thatdata corresponding to the logical address is present in the volatilesemiconductor memory 8 (Yes), the operating system OS writes the data tothe physical address in the volatile semiconductor memory 8corresponding to the logical address by the memory management device 1.

(S304)

Subsequently, in step S304, the memory management device 1 referencesthe address conversion information 13 to set a dirty bit of an entry inthe volatile semiconductor memory 8 corresponding to the address to “1”(End).

(S305)

Subsequently, in step S305, if a determination is made in step S302 thatdata corresponding to the logical address is not present in the volatilesemiconductor memory 8 (No), the memory management device 1 determineswhether data corresponding to the logical address is present in thenonvolatile semiconductor memories 9, 10 by referencing the addressconversion information 13 again.

(S306)

Subsequently, in step S306, if a determination is made in step S305 thatcorresponding data is present in the nonvolatile semiconductor memories9, 10 (Yes), the operating system OS reads the data at the physicaladdress in the nonvolatile semiconductor memories 9, 10 corresponding tothe logical address by the memory management device 1.

(S307)

Subsequently, in step S307, if a determination is made in step S305 thatcorresponding data is not present in the nonvolatile semiconductormemories 9, 10 (No), the operating system OS sends data zero-cleared bythe memory management device 1 to the processor 3 a side, and proceedsto next step S308.

(S308)

Subsequently, in step S308, the memory management device 1 writes thedata read from the nonvolatile semiconductor memory or the zero-cleareddata into the volatile semiconductor memory 8.

(S309)

Subsequently, in step S309, the memory management device 1 sets thephysical address in the volatile semiconductor memory 8 of acorresponding entry of the address conversion information (table) 13,sets a valid/invalid bit in the address conversion information 13 to“1”, and sets a dirty bit to “0”.

(S310)

Subsequently, in step S310, the memory management device 1 writes anupdated data into the volatile semiconductor memory 8, and terminatesthe operation (End).

In the present example, as described above, data present in thenonvolatile semiconductor memories 9, 10 is once read into the volatilesemiconductor memory 8 and then, the data is overwritten with theupdated data. This is intended to prevent the number of times of accessfrom increasing (because reading+writing are needed) if the data isrewritten in the nonvolatile semiconductor memories 9, 10 when the datais written.

<2-3. Operation and Effect>

In the memory management device 1 according to the present example, asdescribed above, in step S012, the operating system OS that receives thememory acquisition request from an application secures a portion of afree logical address. Then, when a writing request occurs, the operatingsystem OS secures a memory region of the more appropriate memory of thevolatile semiconductor memory 8 and the nonvolatile semiconductormemories 9, 10 in accordance with the coloring information accompanyingthe logical address writing count or the like.

Further, the memory management device 1 according to the present examplecreates explicit free space in the volatile semiconductor memory 8 andthus, data in the volatile semiconductor memory 8 to be written into thenonvolatile semiconductor memories 9, 10 is reduced so that the numberof times of accessing the nonvolatile semiconductor memories includingNAND flash memories whose accessible count is limited can be reduced.

Therefore, the memory life of the nonvolatile semiconductor memories 9,10 including NAND flash memories can advantageously be prolonged.

In the present example, it is assumed that the volatile semiconductormemory 8 and the nonvolatile semiconductor memories 9, 10 are managed,as shown in FIG. 4, by a common address conversion table, but thepresent embodiment is not limited to such an example and the volatilesemiconductor memory 8 and the nonvolatile semiconductor memories 9, 10may be managed separately. For example, the volatile semiconductormemory 8 may be managed by a cache tag (table). The cache tag does notnecessarily need to include coloring information.

Fourth Embodiment

A NAND flash memory is generally used as a secondary storage device. Insuch a case, data stored in a NAND flash memory mostly has a data sizeequal to or more than a physical block size. Thus, when a NAND flashmemory is used as a secondary storage device, one block region rarelyhas a plurality of pieces of data with different erasure frequencies.

In contrast, when a NAND flash memory is used as a main memory, asdescribed above, the size of data read from the NAND flash memory andthe size of data written into the NAND flash memory are frequentlyestimated to be less than the physical block size of the NAND flashmemory.

The present embodiment is a modification of the first embodiment and thememory management device 1 that classifies a plurality of pieces ofwrite target data into a plurality of groups (color groups) based oncoloring information and configures data of the block size by puttingthe plurality of pieces of write target data belonging to the same grouptogether will be described.

As the coloring information, for example, at least one of static colorinformation and dynamic color information described in the firstembodiment may be adopted. As the static color information, for example,at least one of “importance”, “reading frequency/writing frequency”, and“data life” may be adopted. As the dynamic color information, forexample, at least one of numbers of times of reading and writing dataand frequencies of reading and writing data may be adopted.

In the present embodiment, a case when the nonvolatile semiconductormemories 9, 10 are NAND flash memories is taken as an example, but thetype of the nonvolatile semiconductor memories 9, 10 is not limited tothis example. An overwrite method will briefly be described here. Theoverwrite method is one writing method of a memory system using a NANDflash memory.

In a NAND flash memory, a page once written cannot be rewritten unless awhole block including the page is erased. In other words, in a NANDflash memory, the same physical address (the physical address of theNAND flash memory, hereinafter, referred to as the NAND physicaladdress) cannot be overwritten unless the physical address is erased.

According to the overwrite method, on the other hand, the correspondencerelationship between the logical address (the logical address of theNAND flash memory, hereinafter, referred to as the NAND logical address)and the NAND physical address is managed by a logical/physicalconversion table and the correspondence relationship can dynamically bechanged. If the overwrite method is adopted, a memory system including aNAND flash memory behaves as if any logical address were overwritablefrom an upper layer.

In the logical/physical conversion table of a NAND flash memory, thecorrespondence relationship between the NAND logical address in units ofblocks (hereinafter, referred to the NLBA) and the NAND physical addressin units of blocks (hereinafter, referred to the NPBA) is managed.Because the logical/physical conversion table of a NAND flash memory ismanaged in units of blocks, even if only data of the size equal to orless than the block size, for example, data for one page is updated,erasure processing of the whole block including the data is needed.

More specifically, if data corresponding to a portion of an NLBA isupdated, a new NPBA is allocated to the NLBA. Update data is writteninto the region corresponding to the new NPBA and at this point,non-updated data stored in the old NPBA is copied to the regioncorresponding to the new NPBA (involved relocation). Incidentally, aplurality of NPBAs may be allocated to one NLBA for data exchange toexecute the data exchanging involved in updating therebetween.

In the present embodiment, a case when write target data is groupedbased on, for example, the static writing frequency SW_color as coloringinformation will be described. However, write target data may also begrouped based on various criteria, for example, the static readingfrequency SR_color, the dynamic writing frequency DW_color, or thedynamic reading frequency DW_color, or further a combination of aplurality of criteria.

In the present embodiment, the management size to group a plurality ofpieces of write target data is less than the block size of a NAND flashmemory. For example, a page equal to the management unit of the coloringtable 14 in size is used as a unit of the management size.

FIG. 43 is a block diagram showing an example of principal portions of afunctional configuration of the memory management device 1 according tothe present embodiment. The coloring information management unit 21includes, in addition to the access frequency calculation unit 24 andthe dynamic color information management unit 25 described withreference to FIG. 2, a group value calculation unit 201 and areservation list management unit 202.

The memory management device 1 further includes the writing managementunit 20, the coloring table 14 stored in the information storage unit17, and a reservation list 32 stored in the working memory 16. Otherfunctional blocks contained in the memory management device 1 are thesame as those described with reference to FIG. 2 and thus, anillustration and description thereof are omitted.

The group value calculation unit 201 references the coloring table 14 tocalculate a color group value based on the static writing frequencySW_color of write target data. The color group value is a valueindicating to which color group of color groups determined in accordancewith the static writing frequency SW_color the write target databelongs. The color group value is calculated based on coloringinformation of the coloring table 14 and shows a grouping result of thewrite target data.

The group value calculation unit 201 calculates a color group value byusing coloring information for each piece of data as an input value, butthe calculation method can be changed in various ways. For example, thegroup value calculation unit 201 may use the static writing frequencySW_color or the dynamic writing frequency DW_color of data directly as acolor group value.

In this case, if the range of the static writing frequency SW_color orthe dynamic writing frequency DW_color is wide, the group valuecalculation unit 201 divides color groups so that the number of colorgroups should not be too many. For example, the group value calculationunit 201 may calculate a color group value based on at least one of thestatic writing frequency SW_color or the dynamic writing frequencyDW_color of data.

The reservation list management unit 202 manages the reservation list 32indicating a reservation state of write target data into a blockallocated to each color group. The reservation list 32 is stored in, forexample, the working memory 16, but may also be stored in anotherstorage unit, for example, the information storage unit 17. Details ofthe reservation list management unit 202 and the reservation list 32will be described later.

The writing management unit 20 references the reservation list 32 towrite data of the block size allocated to a reservation node and puttinga plurality of pieces of write target data together into the blockcorresponding to the reservation node in the nonvolatile semiconductormemories 9, 10.

Differences between writing to a common NAND flash memory and writing bythe memory management device 1 according to the present embodiment willbe described using FIGS. 44 and 45.

FIG. 44 is a diagram showing an example of a data configuration of theblock size when write target data is not classified based on coloringinformation.

In a NAND flash memory adopting the overwrite method, even if only aportion of data in a block is updated, it is necessary to erase thewhole block. Thus, the erasure frequency of the block is proportional todata with the highest access frequency (for example, the static writingfrequency SW_color) of data in the block.

If data with an extremely high access frequency is distributed invarious blocks, block erasure involved in data update work occursfrequently, resulting in an increase in the number of blocks with a higherasure frequency and a shorter life of the NAND flash memory.

In contrast, FIG. 45 is a diagram showing an example of a dataconfiguration of the block size when write target data is classifiedbased on coloring information.

In the present embodiment, as described in the first embodiment,coloring information can be obtained based on the coloring table 14 andthus, write target data can be grouped in accordance with the accessfrequency (for example, the static writing frequency SW_color).

The group value calculation unit 201 classifies write target data lessthan the block size of a NAND flash memory as a color group having acomparable access frequency based on the coloring table 14.

The reservation list management unit 202 puts write target databelonging to the same color group for the block size together to packagethe write target data for a block.

Accordingly, data with a high access frequency can be concentrated in aportion of blocks. Then, it becomes possible to decrease the number ofblocks with a high erasure frequency and prolong the life of the NANDflash memory.

FIG. 46 is a diagram showing an example of a relationship between theaddress conversion information 13 according to the present embodimentand the physical address space of the nonvolatile semiconductor memories9, 10, that is, the NAND logical address.

The address conversion information 13 includes the logical address, thephysical address of the volatile semiconductor memory 8, the physicaladdresses (NAND logical addresses) of the nonvolatile semiconductormemories 9, 10, and valid/invalid flag as items.

If data is stored in the volatile semiconductor memory 8, the physicaladdress of the volatile semiconductor memory 8 is stored by associatingwith the logical address of the data in the address conversioninformation 13.

If data is stored in the nonvolatile semiconductor memories 9, 10, thephysical address (NAND logical addresses) of the nonvolatilesemiconductor memories 9, is stored by associating with the logicaladdress of the data. The valid/invalid flag is a flag indicating whetheror not each entry is valid.

It is assumed that write target data D1 of a color group G2 is firststored in the nonvolatile semiconductor memories 9, 10. In this case,one block of a physical address (NAND logical address) region of thenonvolatile semiconductor memories 9, 10 is reserved for the color groupG2.

Further, a physical address (NAND logical address) P1 of one of alogical address L1 of the write target data D1 and the physical address(NAND logical address) region reserved for the color group G2 and thevalid/invalid flag 1 indicating validity are stored in the addressconversion information 13.

Next, it is assumed that write target data D2 of a color group G4 isstored in the nonvolatile semiconductor memories 9, 10. In this case,one block of a physical address region in the nonvolatile semiconductormemories 9, 10 is reserved for the color group G4.

Then, a physical address Q1 of the logical address of the write targetdata D2 or the physical address region reserved for the color group G4and the valid/invalid flag 1 indicating validity are stored in theaddress conversion information 13.

It is assumed here that write target data D3 belonging to the same colorgroup G2 as the write target data D1 previously stored in the physicaladdress space of the nonvolatile semiconductor memories 9, 10 is storedin the nonvolatile semiconductor memories 9, 10. In this case, thelogical address of the write target data D3, another physical address P2of the physical address region reserved for the color group G2, and thevalid/invalid flag 1 indicating validity are stored in the addressconversion information 13.

FIG. 47 is a diagram showing an example of a logical/physical conversiontable (NAND logical/physical conversion table) 13 a of the nonvolatilesemiconductor memories 9, 10. The NAND logical/physical conversion table13 a is stored in, for example, the information storage unit 17. TheNAND logical/physical conversion table 13 a shows the correspondencebetween the NAND logical block address NLBA and the NAND physical blockaddress NPBA.

In FIG. 47, for example, NPBA2 is allocated to NLBA0, NPBA1 is allocatedto NLBA1, and NPBA0 is allocated to NLBA2. NLBA0 corresponds to, forexample, physical addresses P1, P2, . . . , Pn in the nonvolatilesemiconductor memories 9, 10.

FIG. 48 is a data structure diagram showing an example of thereservation list 32.

The reservation list 32 manages reservation nodes 321 to 326representing physical address regions in units of reserved blockregions. The reservation list 32 has a management section structure toprevent data with a high access frequency and data with a low accessfrequency from being included in the same block. A reservation node ismanaged by, for example, a list structure so that an increase/decreaseof the number thereof can be handled flexibly.

Each of the reservation nodes 321 to 326 includes the color group valueallocated to the respective reservation node, the reserved physicaladdress (reserved NAND logical address), and the free space size.

The reserved physical address is, among physical addresses (NAND logicaladdresses) allocated to reservation nodes, a physical address (NANDlogical address) that is not used and in which data is next to bearranged.

The free space size indicates the size of an unused region of physicaladdress (NAND logical address) regions allocated to reservation nodes.

When new data arises in the logical address space, the reservation listmanagement unit 202 scans the reservation list 32. Next, the reservationlist management unit 202 searches for a reservation node having the samecolor group value as the color group value of the new data and whosefree space size is larger than the size of the new data.

If such a reservation node is searched for, the reserved physicaladdress of the searched reservation node is used as the physical addressof the new data.

The reservation list management unit 202 selects an unused addressregion from the physical address region allocated to the searchedreservation node to update the reserved physical address of the searchedreservation node. The reservation list management unit 202 also reducesthe free space size by the size of the new data to update the free spacesize of the searched reservation node.

If no reservation node is searched for, the reservation list managementunit 202 secures a new physical address region of the block size andadds a new reservation node to the reservation list 32. The reservationlist management unit 202 sets the color group value of the new data asthe color group value of the new reservation node, sets an unusedphysical address of the newly secured physical address region as thereserved physical address of the new reservation node, and sets the sizeof free space of the newly secured physical address region as the freespace size of the new reservation node.

FIG. 49 is a flow chart showing an example of processing of the groupvalue calculation unit 201 and the reservation list management unit 202according to the present embodiment.

In step A1, the group value calculation unit 201 calculates a colorgroup value of the write target data.

In step A2, the reservation list management unit 202 searches thereservation list 32 based on the color group value of the write targetdata.

In steps A3 a and A3 b, the reservation list management unit 202determines whether or not there is an appropriate reservation nodehaving the color group value of the write target data and having freespace equal to or more than the size of the write target data.

If no appropriate reservation node is detected, in step A4, thereservation list management unit 202 references the memory usageinformation 11, the memory specific information 12, and the coloringtable 12 to reserve a new physical address region of the block size fromthe physical address (NAND logical address) space. The reservation listmanagement unit 202 also updates the address conversion information 13by associating the logical address of the write target data with one ofthe physical addresses (for example, the top physical address) of thereserved physical address region via the address management unit 18.

In step A5, the reservation list management unit 202 adds a reservationnode of the reserved one block region to the reservation list 32 andsets the color group value, reservation address, and free space size tothe reservation node. Then, the processing proceeds to step A8 a.

If an appropriate reservation node is detected, in step A6, thereservation list management unit 202 sets the reservation address of theappropriate reservation node as the physical address and updates theaddress conversion information 13 by associating the logical address ofthe write target data with the physical address via the addressmanagement unit 18.

In step A6, the reservation list management unit 202 updates thereservation address of the appropriate reservation node and the freespace size. Then, the processing proceeds to step A8 a.

In steps A8 a and A8 b, the reservation list management unit 202determines whether or not the updated free space size of the appropriatereservation node is smaller than an optional size.

If the free space size is equal to or larger than the optional size, theprocessing ends.

If the free space size is smaller than the optional size, in step A9,the reservation list management unit 202 discards the appropriatereservation node from the reservation list 32, and then the processingends.

FIG. 50 is a diagram showing an example of a state transition of theaddress conversion information 13 in the present embodiment.

In state 1, data for a logical address “0x0010_(—)0000” occurs and thelogical address “0x0010_(—)0000” is registered in the address conversioninformation 13.

The group value calculation unit 201 references the coloring table 14based on the logical address “0x0010_(—)0000” to calculate a color groupvalue for the logical address “0x0010_(—)0000”. The reservation listmanagement unit 202 searches the reservation list 32 based on the colorgroup value.

In this example, it is assumed that no reservation node (range of thephysical address region) corresponding to the color group value isdetected. If no reservation node is found, the reservation listmanagement unit 202 determines a physical address “0x0030_(—)0000” forthe logical address “0x0010_(—)0000” based on the memory usageinformation 11, the memory specific information 12, and the coloringtable 12.

In state 2, the physical address “0x0030_(—)0000” for the logicaladdress “0x0010_(—)0000” is registered in the address conversioninformation 13 by the address management unit 18.

The group value calculation unit 201 reserves an address region for oneblock region from the physical address “0x0030_(—)0000”.

The group value calculation unit 201 adds a reservation nodecorresponding to the reserved address region to the reservation list 32.The group value calculation unit 201 sets the color group valuecalculated in state 1 to the reservation node.

In state 3, data for a logical address “0x0030_(—)0000” occurs and thelogical address “0x0030_(—)0000” is registered in the address conversioninformation 13 by the address management unit 18.

The group value calculation unit 201 references the coloring table 14based on the logical address “0x0030_(—)0000” to calculate a color groupvalue for the logical address “0x0030_(—)0000”. The reservation listmanagement unit 202 searches the reservation list 32 based on the colorgroup value. In this example, it is assumed that a reservation nodecorresponding to the color group value is detected. The reservation listmanagement unit 202 determines a reserved physical address“0x0040_(—)0000” of the detected reservation node as the physicaladdress for the logical address “0x0030_(—)0000”.

In state 4, the physical address “0x0040_(—)0000” for the logicaladdress “0x0030_(—)0000” is registered in the address conversioninformation 13 by the address management unit 18.

In the present embodiment described above, data of the block size isconfigured by a plurality of pieces of write target data belonging to agroup of the same access frequency based on coloring information of theplurality of pieces of write target data.

Therefore, data with a high access frequency can be concentrated in aspecific block so that in the memory management device 1 adopting theoverwrite method, it becomes possible to decrease the number of blockswith a high erasure frequency and prolong the life of the nonvolatilesemiconductor memories 9, 10.

Fifth Embodiment

Generally, the MPU uses a DRAM as a main memory. If such a system isshut down, execution code and data in the main memory and a context of aprocess are stored in the secondary storage device. Thus, when thesystem is reactivated, it is necessary to reload necessary executioncode and data into the memory from the secondary storage device via anI/O interface. Further, each program is initialized again. Thus, theactivation time of the system is frequently long.

To solve this problem, (a) the method (for example, suspend to swap) ofshutting down the system after saving a storage state of the main memoryand the context of process in a swap region (synonymous with thesecondary storage device) and (b) the method (for example, suspend toRAM) to pause in a state without totally turning off the system so thatdata does not disappear from the volatile memory have been proposed.

However, in the case of (a), it is difficult to optimize execution code,data and so forth to be saved in the swap region and the activation timebecomes longer in proportion to the size of execution code, data, or thelike.

In the case of (b), data is in a volatile memory and thus, acurrent-carrying state needs to be maintained. Therefore, a problem thatit is difficult to pause for a long period of time is posed.

In the present embodiment, the memory management device capable ofreducing the time needed for shutdown and activation and storing datawith a high level of safety in consideration of properties of anonvolatile memory will be described.

<Movement of Data when the Information Processing Device 100 is ShutDown>

The fifth embodiment relates to data movement from the volatilesemiconductor memory 8 to the nonvolatile semiconductor memories 9, 10when the information processing device 100 is shut down.

In the memory management device 1, the memory map of the mixed mainmemory 2 is as shown in FIG. 3. When the information processing device100 is operating, data cached by data reading or writing is present inthe volatile semiconductor memory 8 (DRAM region). When the informationprocessing device 100 is shut down, for example, dirty data that isupdated in the volatile semiconductor memory 8 and is not updated in thenonvolatile semiconductor memories 9, 10 is present. Thus, it isnecessary to select and transfer such dirty data to the nonvolatilesemiconductor memories 9, 10.

FIG. 51 shows an example of a dirty bit field DBF of the volatilesemiconductor memory 8 provided in the information storage unit 17. Eachcolumn of the dirty bit field DBF corresponds to index information setbased on a physical address and has flag data indicating whether datathereof is dirty set thereto. Flag data “0” indicates that datacorresponding to the entry thereof has been erased or data thereof hasbeen read into the volatile semiconductor memory 8, but has not yet beenupdated (synchronized) and flag data “1” indicates that thecorresponding data is updated in the volatile semiconductor memory 8 andis not updated in the nonvolatile semiconductor memories 9, 10 (notsynchronized). That is, data corresponding to the entry of the data “1”needs to be transferred to the nonvolatile semiconductor memories 9, 10when shutdown and data corresponding to the entry of the data “0” neednot be transferred to the nonvolatile semiconductor memories 9, 10.

When data read from the nonvolatile semiconductor memories 9, 10 iswritten into the volatile semiconductor memory 8, data is erased fromthe volatile semiconductor memory 8, or an update of data in thevolatile semiconductor memory 8 is reflected in the nonvolatilesemiconductor memories 9, 10, the memory management device 1 sets theflag data of the corresponding entry to “0”.

When data in the volatile semiconductor memory 8 is updated, the memorymanagement device 1 sets the flag data of the corresponding entry to“1”.

The number of entries of the dirty bit field DBF is equal to a valueobtained by dividing the size of the volatile semiconductor memory 8 bythe I/O unit (cache line size=page size).

FIG. 52 shows an example of processing when the information processingdevice 100 is shut down. This processing is performed by, for example,the processing unit 15.

When the information processing device 100 is shut down, first a totalsize SA of data not updated in the nonvolatile semiconductor memories 9,10 is calculated (step IS31). That is, entries of the dirty bit fieldDBF are searched to detect data whose flag data is “1”. The size of thedetected data whose flag data is “1” is totaled to calculate anon-updated data size SA.

Each entry of the dirty bit field DBF is set, as described above, foreach page size of the nonvolatile semiconductor memory. Thus, theupdated data size SA can be determined by counting the number of entrieswhose flag data is “1” and multiplying the counted value by the pagesize.

Next, a free space size SB of the nonvolatile semiconductor memory iscalculated (step IS32). In the present embodiment, when data in thevolatile semiconductor memory 8 is written into the nonvolatilesemiconductor memory when shutdown, the data is written into an SLCregion of the nonvolatile semiconductor memory 9 in consideration offaster writing and reading and the possibility that the data may bestored for a long period of time. More specifically, the data ispreferentially written into, for example, a B region of the SLC regionshown in FIG. 3.

As described above, the memory management device 1 manages writing intothe nonvolatile semiconductor memories 9, 10 based on information of thecoloring table 14. However, shutdown processing according to the presentembodiment ignores the principle and causes, for example, the B regionof the nonvolatile semiconductor memory 9 to preferentially store datafor storage of data by maintaining, for example, high speed and highreliability.

Thus, the free space size of the B region is calculated. The calculationof the free space size is determined based on, for example, the contentof the memory usage information 11.

Then, the calculated non-updated data size SA and the free space size SBof the B region are compared (step IS33). If, as a result, thecalculated non-updated data size SA is equal to or less than the freespace size SB of the B region, non-updated data in the volatilesemiconductor memory 8 is written into the B region of the nonvolatilesemiconductor memory (step IS34). Next, based on the writing into the Bregion, the address management information shown in FIG. 4 is updated(step IS35).

On the other hand, if, in step IS33, the calculated non-updated datasize SA is determined to be larger than the free space size SB of the Bregion, normal write processing is performed. That is, according to theprinciple, data is written by referencing the coloring table 14 (stepIS36). Then, the address management information is updated (step IS37).

According to the present embodiment, the dirty bit field DBF is providedin the information storage unit 17, whether or not data in the volatilesemiconductor memory 8 is updated is managed based on flag data, anddata in the volatile semiconductor memory 8 is transferred to thenonvolatile semiconductor memory 9 based on flag data of the dirty bitfield DBF when the information processing device 100 is shut down.Therefore, non-updated data can reliably be transferred to thenonvolatile semiconductor memory 9 when the shutdown is executed.

Moreover, non-updated data output from the volatile semiconductor memory8 when the shutdown is executed is written into the SLC region of thenonvolatile semiconductor memory 9. Thus, it becomes possible to makewrite processing faster and also maintain reliability for long-termstorage.

<Faster Activation of the Information Processing Device 100>

The fifth embodiment is intended to make activation of the informationprocessing device 100 faster.

If, for example, an animation player and a browser are operating whenshut down and the priority is set so that the animation player is likelyto be scheduled next when the browser is operating, it is consideredpossible to cause the information processing device 100 to operatefaster if code of the animation player with a higher priority has beentransferred to the volatile semiconductor memory 8 after the informationprocessing device 100 being activated.

Thus, in the present embodiment, pre-reading (look-ahead) hintinformation is added to the coloring table 14 for the purpose of makingactivation faster and the information processing device 100 is activatedby using the pre-reading hint information. The pre-reading hintinformation is set to the coloring table 14 when the shutdown isexecuted. That is, the operating system 27 can reduce memory accessoverheads at activation to enable faster activation by storing thepre-reading hint information in the coloring table 14 in a shutdownprocess.

FIG. 53 shows an example of the coloring table 14 applied in the presentembodiment. A field of pre-reading hint information is added to eachentry for the coloring table 14 shown in FIG. 8. The pre-reading hintinformation is, for example, flag data provided in a field of the staticcolor information. The flag data is “0” indicates that datacorresponding to the entry thereof is not read ahead and the flag datais “1” indicates that data corresponding to the entry thereof is readahead. The flag data is not limited to binary data and may bemulti-valued data.

When the information processing device 100 is shut down, the flag dataas the pre-reading hint information is set to the coloring table 14 in,for example, a shutdown process of the operating system 27.

FIG. 54 shows setting processing of pre-reading hint information. Thisprocessing is performed by, for example, the processing unit 15.

When the information processing device 100 is shut down, pre-readinghint information is first added to the address at which code data neededfor activation is stored (step IS41). That is, the flag data “1” is setto the corresponding entry of the coloring table 14 as the pre-readinghint information.

Then, the pre-reading hint information is added to the context of theprocess with the highest priority (step IS42). That is, the flag data“1” is set to the entry corresponding to the context of the process withthe highest priority of the coloring table 14 as the pre-reading hintinformation. Data with a high priority includes, for example,initialization code data of a device, the context of a process with ahigh priority when shut down or the like.

The flag data “0” as pre-reading hint information is set to data whosestatic color information, for example, the static reading frequency(SR_color) is low, even if related to a process with a high priority.For example, an address space to which MPEG data is mapped correspondsto such data and the address space is set so that no pre-reading occurs.

Next, whether pre-reading hint information is added to data of the setsize is determined (step IS43). That is, whether pre-read data exceedsthe size of the volatile semiconductor memory 8 in which the data readahead is stored is determined. The usage size of the volatilesemiconductor memory 8 is set by, for example, the user. Thus, whetherthe set size is exceeded is determined. If, as a result, the set size isnot exceeded, the processing proceeds to step IS42 to perform the aboveoperation. If, as a result of the determination, the set size isdetermined to be exceeded, the processing ends. In this manner,pre-reading hint information is set to the coloring table 14 whenshutdown.

If the information processing device 100 is activated, execution codeexecuted always and data to be read are present in an activation processof the information processing device 100. The operating system 27 canknow execution code executed in an early stage of activation and thedata region.

When the information processing device 100 is activated, data istransferred from the nonvolatile semiconductor memory to the volatilesemiconductor memory in parallel with the activation process by usingpre-reading hint information set to the coloring table 14.

FIG. 55 shows processing of the operating system 27 when activation.

First, the coloring table 14 is searched (step IS51) to read flag dataas pre-reading hint information of entries (step IS52). Next, whetherthe flag data is “1” is determined (step IS53). If, as a result, theflag data is “1”, data corresponding to the entry thereof is read fromthe nonvolatile semiconductor memories 9, 10 (step IS54). That is, datato which pre-reading hint information is attached and having a priorityover other data is transferred from the volatile semiconductor memory 8to the nonvolatile semiconductor memories 9, 10.

If the flag data is “0” in the determination in step IS53, datacorresponding to the entry thereof is not read.

Then, whether the next entry is present in the coloring table 14 isdetermined (step IS55). If, as a result, the next entry is present, thecontrol is moved to step IS51 to repeat the above operation. If the nextentry is not present, the processing ends.

The end condition of processing is not limited to the case when there isno next entry and the processing can be set to end if a write size whenthe volatile semiconductor memory 8 is activated is preset, the writesize is reached. By setting the write size in this manner, free spacecan be secured in the volatile semiconductor memory 8.

According to the present embodiment, pre-reading hint information isadded to the entry of the coloring table corresponding to data likely tobe executed immediately after activation when the information processingdevice 100 is shut down and the pre-reading hint information is searchedto preferentially transfer data from the nonvolatile semiconductormemories 9, 10 to the volatile semiconductor memory 8 when activation.Thus, overheads when activation when reading occurs frequently can bereduced so that the information processing device 100 can be activatedat high speed.

Moreover, only data with a high priority is transferred to the volatilesemiconductor memory 8 and thus, compared with a case when all datapresent in the volatile semiconductor memory 8 when shutdown is savedand recovered when activation, the content in the volatile semiconductormemory 8 can be sorted out and execution processing after activation canbe made faster.

Sixth Embodiment

In the present embodiment, a concrete example of settings of staticcolor information for the coloring table 14 by the memory managementdevice 1 according to the first embodiment will be described.

The operating system 27 sets static color information of the coloringtable 14 shown in FIGS. 5 and 8 to each piece of data.

Setting methods of static color Information for the coloring table 14include [1] a setting based on an extension or a name of a file, [2] asetting based on a name of a directory, [3] a setting based on a shadowfile, [4] a setting using an extension attribute of a file system, [5] asetting based on a header attached to a file of software (for example,an application) or data (for example, video compressed data of MPEG2 orthe like), [6] a setting based on attribute information of a virtualaddress space, [7] a setting based on a usage frequency of a dynamiclink library, [8] a setting based on a compiler, [9] a setting based ona dynamically generated memory region, and [10] a setting using aprofiler. Each of the setting methods will be described below.

[1] The setting based on the extension or the name of the file

For example, the operating system 27 receives a setting of therelationship between the extension of the file using a kernel commandline and static color information from the user (including the programdeveloper). When, for example, static color information “1”, “2” is setto the extensions “jpeg”, “mpeg” respectively, the operating system 27receives a command like “coloring_ext=jpeg:1,mpeg:2”.

Accordingly, the relationship between the extension of the file and thestatic color information is set to the operating system 27. Theoperating system 27 determines the static color information of databased on the extension of the file corresponding to the data (the filein which the data is arranged) and sets the static color information tothe coloring table 14.

Incidentally, for example, the operating system 27 manages mapping dataassociating the data with the file.

For example, the operating system 27 may reference a table associatingthe extension of the file with the static color information.

Also, instead of the relationship between the extension of the file andthe static color information, the relationship between the name of thefile and the static color information may be set.

[2] The setting based on the name of the directory

For example, the operating system 27 receives a setting of therelationship between the name of the directory and the static colorinformation using a kernel command line from the user. When, forexample, static color information “3”, “4” is specified to directories“/tmp”, “/var/log” respectively, the operating system 27 receives acommand like “coloring_dir=/tmp:3,/var/log:4”.

Accordingly, the relationship between the name of the directory and thestatic color information is set to the operating system 27. Theoperating system 27 determines the static color information of databased on the name of the directory in which the file corresponding tothe data is arranged and sets the static color information to thecoloring table 14.

Incidentally, for example, the operating system 27 may reference a tableassociating the name of the directory with the static color information.

[3] The setting based on the shadow file

The relationship between the static color information and the file orthe relationship between the static color information and the directorymay be individually set by the user in the file system.

For example, the user generates a shadow file for a file. The shadowfile is generated by changing an extension of the file corresponding tothe shadow file. For a file “.foo.ext”, for example, a shadow file“.foo.ext.s_color” is generated in the same directory.

Then, the user causes the shadow file to hold the relationship betweenthe static color information and the file. For example, The static colorinformation of the file “.foo.ext” is set into the shadow file“.foo.ext.s_color”.

The operating system 27 determines the static color information of databased on the shadow file of the file corresponding to the data and setsthe static color information to the coloring table 14.

Incidentally, the shadow file may be generated for a directory so thatthe relationship between the static color Information and the directoryis held in the shadow file.

[4] The setting using the extension attribute of the file system

The relationship between the static color information and the file orthe relationship between the static color information and the directoryset by the user in the file system is set by using, for example, theextension attribute of the file system.

The extension attribute is a function to connect metadata that is notinterpreted by the file system with a file or directory by the user. Thestatic color information of the file or directory is set into metadataconnected with the file or directory.

The operating system 27 determines the static color information of thedata based on the metadata connected with the file corresponding to thedata and sets the static color information to the coloring table 14.

The operating system 27 also determines the static color information ofthe data based on the metadata connected with the directory in which thedata is arranged and sets the static color information to the coloringtable 14.

[5] The setting based on the header attached to the file of the softwareor data

The user modifies the header of a software file or data file and setsthe static color information to the header of the file.

The operating system 27 determines the static color information of thedata based on the header of the file corresponding to the data and setsthe static color information to the coloring table 14.

Incidentally, instead of modifying the header of the file, the staticcolor information may be set by using the above shadow file or extensionattribute.

An application file may be divided into a plurality of sections to setstatic color information to each of the plurality of sections.

Control similar to the control of the memory management device 1 canalso be realized for an SSD by generating a SATA vendor extensioncommand used for the SSD and delivering data and static colorinformation to the SSD.

[6] The setting based on the attribute information of the virtualaddress space

FIG. 56 is a block diagram showing an example of a relationship betweena virtual address region in a virtual address space and attributeinformation.

An Application uses virtual address regions J34 a to J34 f in a virtualaddress space J32.

The operating system 27 includes a virtual storage function. Theoperating system 27 manages each of the virtual address regions J34 a toJ34 f by using virtual address region data corresponding to each of thevirtual address regions J34 a to J34 f. Information J33 is informationabout the virtual address space J32 and includes the virtual addressregion data.

The virtual address region data corresponding to each of the virtualaddress regions J34 a to J34 f has a data structure including the startaddress, end address, first attribute information, and second attributeinformation. For example, at least one piece of virtual address regiondata is used for one process.

The start address and end address of each piece of virtual addressregion data show the start address and end address of the correspondingvirtual address region.

The first attribute information of each piece of virtual address regiondata indicates whether the corresponding virtual address region isreadable “r”, writable “w”, executable “x”, or an occupied region “p” ora shared region “s”.

The second attribute information of each piece of virtual address regiondata indicates whether the corresponding virtual address region is aheap region, stack region, or file map region.

In the present embodiment, of the virtual address region datacorresponding to the virtual address regions J34 a to J34 f, the virtualaddress region data J35 c, J35 d corresponding to the virtual addressregions J34 c, J34 d will be selected and described, but other virtualaddress region data has a similar feature.

The virtual address region J34 c is readable, writable, and an occupiedregion and thus, the operating system 27 stores “r”, “w”, and “p” in thefirst attribute information of the virtual address region data J35 c.

The virtual address region J34 c is a heap region and thus, theoperating system 27 stores “1” indicating the heap region in the secondattribute information of the virtual address region data J35 c.

The virtual address region J34 d is readable, executable, and anoccupied region and thus, the operating system 27 stores “r”, “x”, and“p” in the first attribute information of the virtual address regiondata J35 d.

The virtual address region J34 d is a file map region and thus, theoperating system 27 stores “4” indicating the file map region in thesecond attribute information of the virtual address region data J35 d.

FIG. 57 is a flow chart showing an example of setting processing of thesecond attribute information of virtual address region data by theoperating system 27.

In step SE1, the operating system 27 fetches the virtual address regionto be set.

In step SE2, the operating system 27 sets the initial value “0” to thesecond attribute information.

In step SE3, the operating system 27 determines whether or not thevirtual address region is a heap region.

If the virtual address region is a heap region, in step SE4, theoperating system 27 sets “1” to the second attribute information.

In step SE5, the operating system 27 determines whether or not thevirtual address region is a stack region.

If the virtual address region is a stack region, in step SE6, theoperating system 27 sets “2” to the second attribute information.

In step SE7, the operating system 27 determines whether or not thevirtual address region is a map file region.

If the virtual address region is a map file region, in step SE8, theoperating system 27 sets “4” to the second attribute information.

In step SE9, the operating system 27 determines whether or not to setthe second attribute information to another virtual address region.

If the second attribute information should be set to another virtualaddress region, the processing returns to step SE1.

If the second attribute information should not be set to another virtualaddress region, the processing ends.

FIG. 58 is a diagram showing an example of a setting of static colorinformation based on the virtual address region data J35 c.

FIG. 58 shows a case when static color information of the data arrangedin the virtual address region J34 c is set to the coloring table 14based on the virtual address region data J35 c managed by the operatingsystem 27.

The operating system 27 generates and sets to the coloring table 14 thestatic writing frequency SW_color, the static reading frequencySR_color, and data life SL_color for the data in the virtual addressregion J34 c based on the first attribute and the second attribute ofthe virtual address region data J35 c.

If the data in the virtual address region J34 c is allocated to alogical address space, which is a real memory, due to a page fault, theoperating system 27 generates a data generation time ST_color for thedata in the virtual address region J34 c and sets the data generationtime ST_color to the coloring table 14.

Incidentally, the writing count and reading count for the data in thevirtual address region J34 c are updated by the memory management device1.

[7] The setting based on the usage frequency of the dynamic link library

Commands and libraries have dependence relationships. For example, whensome command is executed, the library on which the command is dependentis used.

Thus, according to the method in [7], the score of a command isdetermined in advance and the score of a (dynamically linked) libraryused by the command is determined based on the score of the command. Thescore is assumed to be a value determined based on the usage frequency.In the example in FIGS. 59 and 60 described later, for example, thevalue of the score increases with an increasing usage frequency.

The static writing frequency SW_color and the static reading frequencySR_color for the data contained in a library are set based on the scoreof the library. Incidentally, the score may be determined by using adynamic linker that dynamically links a library. In this case, forexample, the score of each library is incremented each time the libraryis linked by the dynamic linker. More specifically, if the dynamiclinker is used, the score of a library is initialized to 0 in theinitial stage and then, each time the library is linked, the score ofthe linked library is incremented. As a result, a library with anincreasing number of times of being linked has an increasing score.

FIG. 59 is a diagram showing an example of the dependence relationshipsbetween commands and libraries.

In FIG. 59, a command uses at least one library. The score of a commandis preset.

The score of a library is the sum of scores of commands using thelibrary or libraries using the library.

For example, the score of a command “cp” is set to “5”. The command “cp”uses libraries “libacl.so.1” and “libselenux.so.1”.

The scores of the libraries “libacl.so.1” and “libselenux.so.1” are setto the score “5” of the command “cp” using the libraries “libacl.so.1”and “libselenux.so.1”.

The score of a command “bash” is set to “10”. The command “bash” uses alibrary “libncurses.so.5”.

The score of the library “libncurses.so.5” is set to the score “10” ofthe command “bash” using the library “libncurses.so.5”.

A library “libdl.so.2” is used by the libraries “libselenux.so.1” and“libncurses.so.5”.

The library “libdl.so.2” is set to a sum “15” of the scores of thelibraries “libselenux.so.1” and “libncurses.so.5” using the library“libdl.so.2”.

The scores are set to other commands and libraries according to similarrules.

Incidentally, the score of each command can be modified. The method ofinheriting a score can also be modified in various ways. If, forexample, a parent library has a dependence relationship in which thelibrary is branched to a plurality of child libraries (when, forexample, the parent library selects and uses one of the plurality ofchild libraries), the score of a child library may be a value obtainedby dividing the score of the parent library by the number of childlibraries. If the parent library needs the plurality of child librariessimultaneously, the same score as that of the parent library may be setto the child library.

FIG. 60 is a diagram showing an example of the scores of commands andthe scores of libraries. In FIG. 60, the scores of libraries calculatedfollowing the dependence relationships in FIG. 59 are shown.

FIG. 61 is a diagram showing another calculation example of the scoresof libraries based on the scores of commands. In FIG. 61, the dependencerelationship between libraries is not used and the score of each libraryis calculated as a sum of the scores of commands using the library.

FIG. 62 is a diagram showing an example of a setting of static colorinformation using a score of a library.

In FIG. 62, a case when static color information of the data arranged inthe virtual address region J34 d is set to the coloring table 14 basedon the virtual address region data J35 d managed by the operating system27 is shown.

The operating system 27 generates and sets to the coloring table 14 thestatic writing frequency SW_color, the static reading frequencySR_color, and data life SL_color for the data in the virtual addressregion J34 d based on the first attribute and the second attribute ofthe virtual address region data J35 d and the scores of libraries.

If the data in the virtual address region J34 d is allocated to alogical address space due to a page fault, the operating system 27generates the data generation time ST_color for the data in the virtualaddress region J34 d and sets the data generation time ST_color to thecoloring table 14.

Incidentally, the writing count and reading count for the data in thevirtual address region J34 d are updated by the memory management device1.

[8] The setting based on the compiler

A compiler has a function capable of predicting the frequency (usagefrequency) of a variable or the frequency of a function.

The user sets static color information to data containing a variable orfunction based on the frequency of the variable or the frequency of thefunction predicted by the function of the compiler. Accordingly, thestatic color information can be set more finely than in units of files.

As shown in FIG. 63, the compiler can bring user-specified variables orfunctions together in a specific section at compile time.

The user sets static color information to data containing variables andfunctions brought together by the function of the compiler. Accordingly,variables and functions with a comparable frequency can be broughttogether in the same write unit.

FIG. 64 is a diagram showing an example of a setting of static colorinformation using a compiler.

The user predicts the frequency of a variable and the frequency of afunction by using a compiler and divides the compiled software intosections to set static color information to each section.

For example, the operating system 27 sets “low” to the static writingfrequency SW_color and “high” to the static reading frequency SR_colorfor the section containing “exception handler”.

For example, the operating system 27 sets “low” to the static writingfrequency SW_color and “low” to the static reading frequency SR_colorfor the section containing “exception handler”.

[9] The setting based on the dynamically generated memory region

The user sets static color information to a dynamically generated(secured, released) memory region based on the usage frequency obtainedfrom a profiler described later or the predicted usage frequency.

Accordingly, static color information is made settable to data arrangedin a dynamically generated memory region.

FIG. 65 is a diagram showing an example of a setting of static colorinformation based on the usage frequency of a dynamically generatedmemory region.

For example, the operating system 27 sets “low” to the static writingfrequency SW_color and “high” to the static reading frequency SR_colorfor data arranged in a memory region “kernel page table”.

For example, the operating system 27 sets “high” to the static writingfrequency SW_color and “high” to the static reading frequency SR_colorfor data arranged in a memory region “kernel stack”.

For example, the operating system 27 sets “high” to the static writingfrequency SW_color and “high” to the static reading frequency SR_colorfor data arranged in a buffer region of an animation player.

The operating system 27 directly updates the coloring table 14 when amemory region is acquired and released.

The setting of static color information to data arranged in a heapregion or stack region of an application have been described in thefirst embodiment and thus the description thereof is omitted.

A madvise( ) system call advises the kernel how to handle paginginput/output of a memory block of length bytes starting at an addressaddr. By using the system call, how a mapped memory or shared memoryshould be handled can be conveyed from the application to the kernel andthe kernel can accordingly select an appropriate method such as lookingahead and a cache. A function to set static color information of thespecified memory region may be added to the system call. Alternatively,a new system call to set static color information of the specifiedmemory region may be added.

[10] The setting using the profiler

A profiler has a function to acquire, for example, performanceinformation of an application. The performance information containsstatistical Information such as the usage frequency.

The user sets static color information to an application based onperformance information generated by a profiler.

Accordingly, static color information is not set based on the usagefrequency predicted in advance and instead, static color information isset in accordance with an actual usage state.

According to the present embodiment, as described above, setting methodsof static color information are described. Accordingly, static colorinformation used by the memory management device 1 is set to thecoloring table 14 and based on the static color information, the life ofthe nonvolatile semiconductor memories 9, 10 can be prolonged.

Seventh Embodiment

The memory management device 1, the information processing device 100,and memory devices H32 a, H32 b, H32 c according to the presentembodiment will be described with reference to FIG. 66. FIG. 66 is ablock diagram showing an example of the configuration of the memorymanagement device 1, the information processing device 100, and memorydevices H32 a, H32 b, H32 c according to the present embodiment. Thesame reference numerals are attached to the same or similar elements tothose in the first embodiment and the description thereof is omitted. Inthe description in FIG. 66, the processor 3 b of the processors 3 a, 3b, 3 c will representatively be described, but the other processors 3 a,3 c can also be described in the same manner.

The processing unit 15 included in the memory management device 1includes the memory usage information management unit 22, a connectiondetection unit H33, a determination unit H34, a notification unit 35H,and a replacement control unit H36. The memory management information11, the memory specific information 12, the address conversioninformation 13, and the coloring table 14 described above are stored inthe information storage unit 17 included in the memory managementdevice. Further, the processing unit 15 of the memory management device1 is connected to a plurality of connector portions H44 a, H44 b, H44 c.

The memory devices H32 a, H32 b, H32 c include memory units H37 a, H37b, H37 c, normal notification units H38 a, H38 b, H38 c, warningnotification units H39 a, H39 b, H39 c, usage stop notification unitsH40 a, H40 b, H40 c, and connection operation units H41 a, H41 b, H41 crespectively. Further, the memory devices H32 a, H32 b, H32 c includeconnector units H42 a, H42 b, H42 c respectively. Management informationH43 a, H43 b, H43 c is stored in the memory units H37 a, H37 b, H37 crespectively. Details of the management information H43 a, H43 b, H43 cwill be described later.

The connector units H42 a, H42 b, H42 c included in the memory devicesH32 a, H32 b, H32 c are connected to connector units H44 a, H44 b, H44 crespectively.

Next, the configuration of the memory management device 1 will bedescribed in more detail. In the description that follows, the memorydevice H32 a of the memory devices H32 a, H32 b, H32 c willrepresentatively be described, but the other memory devices H32 b, H32 ccan also be described in the same manner.

The connection detection unit H33 detects connection between the memorymanagement device 1 and the memory device H32 a. When a “mountingnotification” described later is received from the connection operationunit H41 a of the memory device H32 a, the connection detection unit H33detects that the memory device H32 a is electrically connected to thememory management device 1 (a “connected state” is detected). When a“removal notification” described later is received from the connectionoperation unit H41 a of the memory device H32 a, the connectiondetection unit H33 detects that the memory device H32 a is electricallyremoved from the memory management device 1 (a “removal ready state” isdetected).

The determination unit H34 determines the usage state of the memorydevice H32 a based on the memory usage information 11. The usage stateincludes, for example, “normal state”, “warning state”, and “usagestopped state”. The determination unit H34 determines the usage state ofthe memory device H32 a, for example, periodically. The determinationunit H34 also determines the usage state of the memory device H32 a, forexample, each time the memory device H32 a is accessed. The method ofdetermining the usage state will be described later.

The notification unit H35 notifies the memory device H32 a of the usagestate based on the usage state determined by the determination unit H34.

When the connection detection unit H33 detects the “connected state”based on the “mounting notification” from the connection operation unitH41 a of the memory device H32 a, the replacement control unit H36 readsand stores in the memory usage information 11 the erasure count, writingoccurrence count, and reading occurrence count for each predeterminedregion of the memory unit H37 a contained in the management informationH43 a stored in the memory unit H37 a. When the connection detectionunit H33 detects the “removal ready state” based on the “removalnotification” from the connection operation unit H41 a of the memorydevice H32 a, the replacement control unit H36 reads and stores in themanagement information H43 a of the memory unit H37 a the erasure count,writing occurrence count, and reading occurrence count for eachpredetermined region of the memory device H32 a contained in the memoryusage information 11 stored in the information storage unit 17. Detailsof the management information H43 a will be described later.

If the memory device H32 a is, for example, a NAND flash memory, forexample, the erasure count is managed in units of block regions and thewriting occurrence count and reading occurrence count are managed inunits of page regions.

Next, the configuration of the memory devices H32 a, H32 b, H32 c willbe described.

The memory unit H37 a is an SLC type NAND flash memory or an MLC typeNAND flash memory and corresponds to the nonvolatile semiconductormemories 9, 10 in the first embodiment. The memory unit H37 a may be anSLC type NAND flash memory (SLC region) in a portion of regions thereofand an MLC type NAND flash memory (MLC region) in the region excludingthe SLC region. In this case, the SLC region corresponds to thenonvolatile semiconductor memory 9 and the MLC region corresponds to thenonvolatile semiconductor memory 10.

When a notification of “normal state” is received from the notificationunit H35 of the memory management device 1, the normal notification unitH38 a displays the normal state. For example, the normal notificationunit H38 a is an emitter of the first color (blue) and displays thenormal state by being lit.

When a notification of “warning state” is received from the notificationunit H35 of the memory management device 1, the warning notificationunit H39 a displays the warning state. For example, the warningnotification unit H39 a is an emitter of the second color (yellow) anddisplays the warning state by being lit.

When a notification of “usage stopped state” is received from thenotification unit H35 of the of the memory management device 1, theusage stop notification unit H40 a displays the stopped state. Forexample, the usage stop notification unit H40 a is an emitter of thethird color (red) and displays the usage stopped state by being lit.

When the memory device H32 a is electrically disconnected (removed) fromthe memory management device 1, the connection operation unit H41 anotifies the memory management device 1 that the memory device H32 a hasbeen removed (removal notification). The connection operation unit H41 aincludes, for example, an electric or mechanical button and, when thememory device H32 a is removed, makes a removal notification to thememory management device 1 by the button being pressed by the user.

When the memory device H32 a is electrically connected to the memorymanagement device 1, the connection operation unit H41 a notifies thememory management device 1 that the memory device H32 a has beenconnected (mounting notification). When electrically connecting thememory device H32 a to the memory management device 1, for example, amounting notification is made to the memory management device 1 by thebutton being pressed by the user.

The memory device H32 a and the memory management device 1 areelectrically connected by the connector unit H42 a being connected tothe connector unit H44 a.

Next, changes of the erasure count of the memory unit H37 a included inthe memory device H32 a will be described with reference to FIG. 67.FIG. 67 is a graph showing an example of changes of the erasure count ofthe memory unit H37 a. The horizontal axis thereof represents the timeand the vertical axis thereof represents the erasure count.

The memory unit H37 a of the memory device H32 a is accessed (read,written, erased) by the processor 3 b. Thus, the erasure count, writingoccurrence count, and reading occurrence count of the memory unit H37 aincrease with the passage of time and the erasure count reaches theerasable upper limit count of the memory unit H37 a at some time. Whenthe erasure count of the memory unit H32 a reaches the erasable upperlimit count, writing, reading, and erasure of data with respect to thememory unit H32 a are not desirable from the viewpoint of reliability.

The memory management device 1 manages, as described above, the erasurecount, writing occurrence count, and reading occurrence count of thenonvolatile semiconductor memories 9, 10 (memory device H32 a) throughthe memory usage information 11. In the present embodiment, as will bedescribed below, the memory management device 1 monitors the usage stateof the memory device H32 a based on the memory usage information 11 andwarns the memory device H32 a before the erasure count of the memoryunit H32 a reaches the erasure occurrence upper limit count.

The determination of the usage state of the memory device H32 a based onthe erasure count of the memory device H32 a will be described withreference to FIG. 68. FIG. 68 is a graph showing an example of the usagestate of the memory device H32 a based on the erasure count of thememory device H32 a. The horizontal axis thereof represents the time andthe vertical axis thereof represents the erasure count. Incidentally,writing can also be used, like the erasure, for determination of theusage state of the memory device H32 a.

FIG. 68 shows an example of changes of the erasure count of the memoryunit H37 a by a broken line. A regression curve ΔtERASE (for example, aprimary regression curve) for the erasure count of the memory unit H37 ais shown as a solid line. An erasure count ERASE_(alert) after apredetermined time (warning period) tERASE_(before) from the currenttime is predicted from the primary regression curve. If ERASE_(alert)exceeds the erasable upper limit count ERASE_(max), the usage state ofthe memory unit H37 a is determined to be “warning state”.IfERASE_(alert) does not exceed the erasable upper limit countERASE_(max), the usage state of the memory unit H37 a is determined tobe “normal state”. If the erasure count at the current time exceeds theerasable upper limit count ERASE_(max), the usage state of the memoryunit H37 a is determined to be “usage stopped state”.

If, as described above, the memory unit H37 a is a NAND flash memory,the erasure count of the memory unit H37 a is managed in units of blockregions. The memory unit H37 a contains a plurality of block regions.Variations of the erasure count between the plurality of block regionscontained in the memory unit H37 a are small due to wear leveling. Thus,for example, the average value of the erasure count of each of theplurality of block regions contained in the memory unit H37 a is set asthe erasure count of the memory unit H37 a. Alternatively, for example,the maximum erasure count of the plurality of block regions contained inthe memory unit H37 a may be set as the erasure count of the memory unitH37 a. This also applies to the reading occurrence count and writingoccurrence count.

Next, the determination of the usage state of the memory device H32 abased on the reading occurrence count of the memory device H32 a will bedescribed with reference to FIG. 69. FIG. 69 is a graph showing anexample of the usage state of the memory device H32 a based on thereading occurrence count of the memory device H32 a. The horizontal axisthereof represents the time and the vertical axis thereof represents thereading occurrence count.

FIG. 69 shows an example of changes of the reading occurrence count ofthe memory unit H37 a by a broken line. A regression curve ΔtREAD (forexample, a primary regression curve) for the reading occurrence count ofthe memory unit H37 a is shown as a solid line. A reading occurrencecount READ_(alert) after a predetermined time (warning period)tREAD_(before) from the current time is predicted from the primaryregression curve. If READ_(alert) exceeds the readable upper limit countREAd_(max), the usage state of the memory unit H37 a is determined to be“warning state”. If READ_(alert) does not exceed the erasable upperlimit count READ_(max), the usage state of the memory unit H37 a isdetermined to be “normal state”. If the reading occurrence count at thecurrent time exceeds the readable upper limit count READ_(max), theusage state of the memory unit H37 a is determined to be “usage stoppedstate”.

Next, an example of processing to notify the memory device H32 a of theusage state based on the erasure count of the memory device H32 a willbe described with reference to FIG. 70. FIG. 70 is a flow chart showingan example of notifying the memory device H32 a of the usage state basedon the erasure count of the memory device H32 a.

In step HA1, the memory usage information management unit 22 reads thememory usage information 11.

In step HA2, the memory usage information management unit 22 reads theerasure count of the memory device H32 a at the current time from thememory usage information 11.

In step HA3, the determination unit H34 calculates new ΔtERASE based onthe current time, a time prior to the current time, the erasure count atthe current time, the erasure count at the time prior to the currenttime, and past ΔtERASE stored in the memory usage information 11. Forexample, the determination unit H34 calculates ΔtERASE, which is theerasure count per unit time, based on the erasure start time, thecurrent time, and the erasure count at the current time.

In step HA4, the determination unit H34 determines whether the erasurecount at the current time is equal to or less than the erasable upperlimit count ERASE_(max).

If the erasure count at the current time exceeds the erasable upperlimit count ERASE_(max), in step HA5, the determination unit H34determines that the memory device H32 a is in the usage stopped stateand the processing proceeds to step HA9.

If the erasure count at the current time is equal to or less than theerasable upper limit count ERASE_(max), in step HA6, the determinationunit H34 calculates ΔtERASE×tERASE_(before)+erasure count at the currenttime to determine a predicted value ERASE_(alert) the erasure countafter tERASE_(before) passes from the current time.

In step HA7, the determination unit H34 determines whether the predictedvalue ERASE_(alert) is equal to or less than the erasable upper limitcount ERASE_(max).

If the predicted value ERASE_(alert) exceeds the erasable upper limitcount ERASE_(max), in step HA8, the determination unit H34 determinesthat the memory device H32 a is in the warning state and the processingproceeds to step HA9.

If the predicted value ERASE_(alert) is equal to or less than theerasable upper limit count ERASE_(max), the processing proceeds to stepHA9.

In step HA9, the determination unit H34 updates the memory usageinformation 11 by storing the erasure count at the current time andΔtERASE.

By notifying the memory device H32 a of the usage state based on theerasure count of the memory device H32 a, a warning can be given beforethe usage state of the memory device H32 a becomes “usage stoppedstate”.

Next, an example of processing to notify the memory device H32 a of theusage state based on the reading occurrence count of the memory deviceH32 a will be described with reference to FIG. 71. FIG. 71 is a flowchart showing an example of notifying the memory device H32 a of theusage state based on the reading occurrence count of the memory deviceH32 a.

Steps HB1 to HB9 in FIG. 71 are the same as steps HA1 to HA9 in FIG. 70whose determination object is the erasure count except that thedetermination object is the reading occurrence count and thus, thedescription thereof is omitted.

By notifying the memory device H32 a of the usage state based on thereading occurrence count of the memory device H32 a as described above,a warning can be given before the usage state of the memory device H32 abecomes “usage stopped state”.

In the present embodiment described above, if the predicted erasurecount ERASE_(alert), READ_(alert) after the predetermined timetERASE_(before), tREAD_(before) from the current time exceeds theerasable upper limit count ERASE_(max), the readable upper limit countREAD_(max) respectively, the warning state is set. However, the abovedetermination processing can be modified in various ways. A modificationof the determination processing in the present embodiment will bedescribed below.

For example, the determination unit H34 calculates ΔtERASE.

The determination unit H34 determines a time tERASE_(max) at which theerasure count is predicted to reach ERASE_(max) based on the erasurecount at the current time, ΔtERASE, and ERASE_(max).

The determination unit H34 determines a time tERASE_(alert) at which thewarning state should be set by subtracting tERASE_(before) fromtERASE_(max).

Then, if the current time reaches or passes the time tERASE_(alert) atwhich the warning state should be set, the determination unit H34determines that the usage state is the warning state. Alternatively, thedetermination unit H34 determines the erasure count ERASE_(alert) atwhich the warning state should be set based on the erasure start time,ΔtERASE, and the time tERASE_(alert) at which a warning should be givenand determines that the usage state is the warning state when theerasure count becomes equal to or more than the erasure countERASE_(alert) at which the warning state should be set.

This also applies when, instead of the erasure count, the readingoccurrence count is the object of determination.

Next, the management information H43 a stored in the memory device H32 awill be described with reference to FIG. 72. FIG. 72 is a diagramshowing an example of data included in the management information H43 a.

The management information H43 a contains the erasure count for eachpredetermined region of the memory unit H37 a of the memory device H32a, the regression curve ΔtERASE for the erasure count, the erasableupper limit count ERASE_(max), the warning period tERASE_(before), andthe erasure start time. Further, the management information H43 acontains the reading occurrence count for each predetermined region ofthe memory unit H37 a of the memory device H32 a, the regression curveΔtREAD for the reading occurrence count, the erasable upper limit countREAD_(max), the warning period tREAD_(before), and the read start time.

The erasure count, the reading occurrence count, and the regressioncurves ΔtERASE, ΔtREAD are information managed by the memory usageinformation 11 of the memory management device 1 and are stored, as willbe described later, in the management information H43 a when the memorydevice H32 a is removed from the memory management device 1.

Next, processing after the memory device H32 a is electrically connectedto the memory management device 1 until access to the memory device H32a is started will be described with reference to FIG. 73. FIG. 73 is aflow chart showing an example of processing after the memory device H32a is electrically connected to the memory management device 1 untilaccess to the memory device H32 a is started.

First, in step HC1, the connection detection unit H33 of the memorymanagement device 1 detects that the memory device H32 a is electricallyconnected (connected state) to the memory management device 1 byreceiving a “mounting notification” from the memory device H32 a.

Next, in step HC1, the memory management device 1 determines whether themanagement information H43 a is stored in the memory device H32 a. Ifthe management information H43 a is stored in the memory device H32 a,the processing proceeds to step HC3. If the management information H43 ais not stored in the memory device H32 a, the processing proceeds tostep HC4.

In step HC3, the memory management device 1 reads and stores in thememory usage information 11 the erasure count, writing occurrence count,and reading occurrence count for each predetermined region of the memoryunit H37 a contained in the management information H43 a. The memorymanagement device 1 also reads and stores in the memory specificinformation 12 the erasable upper limit count ERASE_(max), the readableupper limit count READ_(max), and the warning periods tERASE_(before),tREAD_(before) of the memory unit H37 a contained in the managementinformation H43 a.

In step HC4, the memory management device 1 generates the new managementinformation H43 a, writes the new management information H43 a into thememory unit H37 a, and stores “0” in the memory usage information 11 asthe values of the erasure count, writing occurrence count, and readingoccurrence count for each predetermined region.

Access to the memory device H32 a is started after the processing instep HC3 or HC4. If access to the memory device H32 a occurs, asdescribed above, the erasure count, writing occurrence count, andreading occurrence count for each predetermined region of the memoryusage information 11 corresponding to the memory device H32 a areupdated.

Next, processing after the memory management device 1 receives a“removal notification” from the memory device H32 a until the memorydevice H32 a becomes removable with reference to FIG. 74. FIG. 74 is aflow chart showing processing after the memory management device 1receives a “removal notification” from the memory device H32 a until thememory device H32 a becomes removable.

First, in step HD1, the connection detection unit H33 of the memorymanagement device 1 receives a “removal notification” from the memorydevice H32 a.

Next, in step HD2, the replacement control unit H36 of the memorymanagement device 1 reads data stored in the memory device H32 a fromthe memory device H32 a and writes the data into another memory device(for example, the memory device H32 b).

Next, in step HD3, the replacement control unit H36 stores the writingoccurrence count, read occurrence count, and erasure count for eachpredetermined region of the memory device H32 a managed by the memorymanagement device 1 in the memory unit H37 a of the memory device H32 aas the management information H43 a.

Next, in step HD4, the notification unit H35 of the memory managementdevice 1 notifies the memory device H32 a that the memory device H32 acan be removed.

As described above, usage information of the memory device H32 a can beacquired by storing the writing occurrence count, reading occurrencecount, and erasure count for each predetermined region of the memorydevice H32 a in the memory unit H37 a of the memory device H32 a as themanagement information H43 a when the memory device H32 a is removed andnext, reading the management information H43 a when the memory deviceH32 a is mounted.

Next, a replacement state of the memory device will be described withreference to FIG. 75. FIG. 75 is a diagram showing an example of thereplacement state of the memory device.

The information processing device 100 includes the processor 3 b, thememory management device 1, and memory devices H32 a to H321. Theinformation processing device 100 applies RAID technology to the memorydevices H32 a to H321. Further, in the present embodiment, the memorymanagement device 1 that controls access to the memory devices H32 a toH321 supports hot swapping of hardware. The information processingdevice 100 is assumes to be an device that needs to continuous operationsuch as a server device.

The memory devices H32 a to H32 m have upper limits of the memoryreading count and memory erasure count and are replaced when the end oflife thereof is reached. The memory devices H32 a to H32 m includedisplay units H45 a to H45 m respectively. In FIG. 75, the display unitsH45 a to H45 m emit light, for example, in green when the memory devicesH32 a to H32 m are in a normal state and emit light, for example, in redwhen the memory devices H32 a to H32 m are in a warning state or usagestopped state.

Buttons H46 a to H461 are allocated to the mounted memory devices H32 ato H321 respectively.

By applying RAID technology to the memory management device 1, even ifone (the memory device H32 k in FIG. 75) of the memory devices H32 a toH321 is in a warning state or usage stopped state, the informationprocessing device 100 can be operated normally by the memory devices H32a to H32 j and the memory device H321 that remain. Then, the user canremove the memory device H32 k in the warning state or usage stoppedstate and mount the spare memory device H32 m while the informationprocessing device 100 is operating.

If, for example, the memory device H32 k is used and the readingoccurrence count or the erasure count of the memory device H32 kincreases to approach the readable upper limit count or the erasableupper limit count respectively, the display unit H45 k of the memorydevice H32 k emits light in red. To replace the mounted memory deviceH32 k, the user presses the corresponding button H46 k. When the buttonH46 k is pressed, a removal notification is sent to the memorymanagement device 1. After the removal notification is received, thememory management device 1 performs processing such as saving data inthe memory device H32 k and turning off the memory device H32 k.

If only data whose importance is equal to or less than a specificthreshold is stored in the memory device H32 k to be removed, the memorydevice H32 k may immediately be replaced without the data being saved.

If the memory device H32 k becomes removable, the user removes thememory device H32 k and mounts the new memory device H32 m.

The memory device H32 k is used as a main storage device of theinformation processing device 100, for example, a server device,personal computer, or game machine and even if the memory device H32 kenters the warning state, the memory device H32 k can be reused, forexample, as a medium like an alternative of CD-R or a photo-recordingmedium of a digital camera.

In the present embodiment, to make the old memory device H32 k usable inanother Information processing device, management information of thememory device H32 k is stored in the memory device H32 k and further,the display unit H45 k is included in the memory device H32 k.

Displays units for electronic ink may be used as the display units H45 ato H45 m. For example, the determination unit H34 of the memorymanagement device 1 determines the access state (for example, “erasurecount/erasable upper limit count”, “reading occurrence count/readableupper limit count” and the like) to each of the memory devices H32 a toH321 based on the memory usage information 11 and the memory specificinformation 12. The notification unit H35 of the memory managementdevice 1 controls the display of the display units H45 a to H451 forelectronic ink based on the access state to each of the memory devicesH32 a to H321. For example, the display units H45 a to H451 show theaccess state as a bar graph.

Display content of the display units H45 a to H451 for electronic ink ismaintained even if the memory devices H32 a to H321 are removed from thememory management device 1. Thus, after removing the memory devices H32a to H321, the user can mount the memory devices H32 a to H321 onanother information processing device for reuse with reference todisplay content of the display units H45 a to H451 for electronic ink.

Next, the reuse of the memory device H32 a will be described withreference to FIG. 76. FIG. 76 is a block diagram showing an example ofthe reuse of the memory device H32 a.

The memory management device 1 is assumed to be an device like a serverdevice and personal computer from which high reliability is demanded fordata storage and access.

For example, an information processing device 100A is assumed to be andevice like a digital camera, printer, and mobile phone from which highreliability demanded from the information processing device 100 is notdemanded for data storage and access.

Normal operation is desired for the information processing device 100and thus, the memory device H32 a is replaced at an early point in timeafter a warning is issued.

In the information processing device 100A, by contrast, the memorydevice H32 a can be used until a usage stop notification arises evenafter a warning is issued.

When the memory device H32 a is notified of a warning in the informationprocessing device 100, the user can remove the memory device H32 a fromthe information processing device 100 and mount the memory device H32 aon the information processing device 100A for use. In this manner, thememory device H32 a can be effectively utilized.

Next, the method of selecting the writing destination from the memorydevices H32 a, H32 b, H32 c based on coloring information so thatwarning periods of the memory devices H32 a, H32 b, H32 c should not beconcentrated in a short period of time will be described with referenceto FIG. 77.

As shown in FIG. 77, the writing management unit 20 exercises control sothat data with high static color information or data with high dynamiccolor information is written into the specific memory device H32 a ofthe memory devices H32 a, H32 b, H32 c based on coloring information.Accordingly, the access count (the erasure count, reading occurrencecount, and writing occurrence count) to the memory device H32 aincreases earlier than the other memory devices H32 b, H32 c.

Accordingly, the specific memory device H32 a enters the warning stateearlier so that concentration of the warning period in a short period oftime can be suppressed and an increase in work load such as replacingmany memory devices in a short period of time can be prevented.

In the present embodiment described above, the memory devices H32 a toH321 whose access count has an upper limit can easily be mounted on thememory management device 1 and further can easily be removed.

Therefore, state monitoring and maintenance of the memory devices H32 ato H321 used in the information processing device 100 can easily beimplemented.

In the present embodiment, the memory devices H32 a to H321 can beswapped while the information processing device 100 being continuouslyoperated.

Further, in the present embodiment, the memory devices H32 a to H321that can be mounted on and removed from the memory management device 1can be reused.

In the present embodiment, a high-reliability, high-speed, andlarge-capacity storage device combining the memory devices H32 a to H321can be realized and the memory devices H32 a to H321 can easily bereplaced so that the utilization rate of the information processingdevice 100 can be improved.

Eighth Embodiment

The present embodiment is a modification of the first embodiment. Amemory management device according to the present embodiment candynamically switch the SLC region in the nonvolatile semiconductormemories 9, to the MLC region and further can switch the MLC region tothe SLC region.

In the present embodiment, the SLC region refers to a memory region usedas an SLC type NAND flash memory in the nonvolatile semiconductormemories 9, 10. The MLC region refers to a memory region used as an MLCtype NAND flash memory in the nonvolatile semiconductor memories 9, 10.

The nonvolatile semiconductor memories 9, 10 may be an SLC region or anMLC region in the whole memory region of the nonvolatile semiconductormemories 9, 10 or a portion of the memory region of the nonvolatilesemiconductor memories 9, 10 may be an SLC region and the memory regionthat is not the SLC region may be an MLC region.

Information about whether the memory region of the nonvolatilesemiconductor memories 9, 10 is an SLC region or an MLC region(hereinafter, referred to as “SLC/MLC region information”) is managedby, for example, the memory specific information 12. For example, thememory specific information 12 holds information about whether thememory region specified by a physical address is an SLC region or an MLCregion in the nonvolatile semiconductor memories 9, 10. While theSLC/MLC region information for each memory region is assumed to bemanaged by the memory specific information 12, but may also be managedby the memory usage information 11.

FIG. 78 is a diagram showing an example of the configuration of thememory management device according to the present embodiment.

A memory management device D32 includes a processing unit D33, theworking memory 16, and the information storage unit 17.

The processing unit D33 includes a wear-out rate calculation unit D34, aswitching determination unit D35, and a switching control unit D36.Further, the processing unit D33 includes, like the processing unit 15in the first embodiment described above, the address management unit 18,the reading management unit 19, the writing management unit 20, thecoloring information management unit 21, the memory usage informationmanagement unit 22, and the relocation unit 23, but these units areomitted in FIG. 78.

The memory management device D32 in the present embodiment can switchthe SLC region to the MLC region based on information about the wear-outrate of the SLC region in the nonvolatile semiconductor memories 9, 10.Further, the memory management device D32 can switch the MLC region tothe SLC region based on information about the wear-out rate of the MLCregion in the nonvolatile semiconductor memories 9, 10. The wear-outrate is a ratio of the writing count to the writable upper limit countof the memory region.

The memory management device D32 can similarly switch the SLC region andthe MLC region dynamically based on an erasure wear-out rate, which isthe ratio of the erasure count to the erasable upper limit count, and aread wear-out rate, which is the ratio of the reading count to thereadable upper limit count. Further, the memory management device D32can switch the SLC and the MLC dynamically based on at least two of thewrite wear-out rate, erasure wear-out rate, and read wear-out rate.

The wear-out rate calculation unit D34 references the memory usageinformation 11 and the memory specific information 12 to calculate thewrite wear-out rate of a memory region based on the writing count andthe writable upper limit count of the memory region. Similarly, thewear-out rate calculation unit D34 can calculate the read wear-out rateand the erasure wear-out rate by referencing the memory usageinformation 11 and the memory specific information 12. The writewear-out rate and the read wear-out rate are calculated, for example, inunits of page region or block region. The erasure wear-out rate iscalculated, for example, in units of block region.

For a memory region in which, for example, the SLC region and the MLCregion are larger than the block region, the write wear-out rate iscalculated for each of a plurality of block regions contained in the SLCregion or the MLC region. Variations of the write wear-out rate aresmall between the plurality of block regions contained in the SLC regionor the MLC region by wear leveling. Thus, for example, the average valueof the write wear-out rates of the plurality of block regions containedin the SLC region or the MLC region is set as the write wear-out rate ofthe SLC region or the MLC region. Alternatively, for example, themaximum write wear-out rate of the write wear-out rates of the pluralityof block regions contained in the SLC region or the MLC region may beset as the write wear-out rate of the SLC region or the MLC region. Thisalso applies to the read wear-out rate and the erasure wear-out rate.

The switching determination unit D35 determines whether the writewear-out rate of the SLC region exceeds the threshold (hereinafter,referred to as the “SLC threshold”) of the write wear-out rate set tothe SLC region. The switching determination unit D35 also determineswhether the write wear-out rate of the MLC region exceeds the threshold(hereinafter, referred to as the “MLC threshold”) of the write wear-outrate set to the MLC region. Information of the SLC threshold and the MLCthreshold of each memory region is managed by the memory specificinformation 11.

If the write wear-out rate of the SLC region exceeds the SLC threshold,the switching control unit D36 exercises control to switch the SLCregion to the MLC region. If the write wear-out rate of the MLC regionexceeds the MLC threshold, the switching control unit D36 exercisescontrol to switch the MLC region to the SLC region. Further, theswitching control unit D36 updates “SLC/MLC region information” managedby the memory specific information 11 in accordance with switching ofthe SLC region and the MLC region.

If switching from the SLC region to the MLC region occurs, the switchingcontrol unit D36 exercises control to switch one of MLC regions to theSLC region. If switching from the MLC region to the SLC region occurs,the switching control unit D36 also exercises control to switch one ofMLC regions to the SLC region. Accordingly, the switching control unitD36 exercises control to minimize a change in the ratio of the SLCregions and MLC regions before and after switching of memory regions bythe switching control unit D36. Incidentally, the SLC region and the MLCregion are switched by memory regions to be switched in the nonvolatilesemiconductor memories 9, 10 being determined and a command being issuedby the switching control unit D36.

Further, if data is stored in memory regions to be switched, theswitching control unit D36 moves data and updates the address conversioninformation 13 in accordance with the movement of data.

Moreover, the memory usage information management unit 22 updates thememory usage information 11 (such as the writing count, erasure count,and reading count) of switched memory regions in accordance withswitching of the SLC region and the MLC region by the switching controlunit D36.

FIG. 79 is a schematic diagram showing a first example of dynamicswitching of nonvolatile semiconductor memories according to the presentembodiment. The nonvolatile semiconductor memories 291 to 294 shown inFIG. 79 correspond to the nonvolatile semiconductor memories 9, 10 andare used as the main memory of the information processing device 100.

In the example shown in FIG. 79, all memory regions of the nonvolatilesemiconductor memories 291 to 293 are used as an SLC region (thenonvolatile semiconductor memories 291 to 293 are SLC type NAND flashmemories). Moreover, all memory regions of the nonvolatile semiconductormemory 294 are used as an MLC region (the nonvolatile semiconductormemory 294 is an MLC type NAND flash memory). The nonvolatilesemiconductor memories 291 to 294 are, for example, memory cards.

As described in the first embodiment, data with a high access frequencyis written into the SLC type nonvolatile semiconductor memories 291 to293. Thus, the write wear-out rate of the SLC type nonvolatilesemiconductor memories 291 to 293 increases. On the other hand, datawith a low access frequency is written into the MLC type nonvolatilesemiconductor memory 294. Thus, the write wear-out rate of the MLC typenonvolatile semiconductor memory 294 decreases.

If the switching determination unit D35 determines that the writewear-out rate of the nonvolatile semiconductor memory 291 has exceededthe SLC threshold of the nonvolatile semiconductor memory 291, theswitching control unit D36 switches the nonvolatile semiconductor memory291 from the SLC type to the MLC type. Further, the switching controlunit D36 switches the nonvolatile semiconductor memory 294 with a lowwrite wear-out rate from the MLC type to the SLC type. Accordingly, thenonvolatile semiconductor memory 291 with a high write wear-out rate isused as the MLC type and data with a low access frequency is writtenthereinto. On the other hand, the nonvolatile semiconductor memory 294with a low write wear-out rate is used as the SLC type and data with ahigh access frequency is written thereinto. The life of the MLC typenonvolatile semiconductor memory 291 (period in which the MLC typenonvolatile semiconductor memory 291 can be used as the main memory) canbe prolonged by applying strong ECC (Error-Correcting Code) to the MLCtype nonvolatile semiconductor memory 291. If strong ECC is applied, thereading speed at which data is read from a nonvolatile semiconductormemory generally falls, but the reading speed from a nonvolatilesemiconductor memory may be low in the present embodiment and thus,strong ECC can be used.

Further, if the write wear-out rate of the nonvolatile semiconductormemories 291 to 294 increases to make it difficult to use the memories291 to 294 as the main memory, the nonvolatile semiconductor memories291 to 294 may be removed from the information processing device 100 touse the memories 291 to 294 for an application with a low writingfrequency such as CD-R use.

FIG. 80 is a schematic diagram showing a second example of dynamicswitching of nonvolatile semiconductor memories according to the presentembodiment. A nonvolatile semiconductor memory 295 shown in FIG. 80corresponds to the nonvolatile semiconductor memories 9, 10 and is usedas the main memory of the information processing device 100. In theexample shown in FIG. 80, the nonvolatile semiconductor memory 294 iscomposed of memory regions used as an SLC region and memory regions usedas an MLC region.

Also in the example shown in FIG. 80, as described in the example shownin FIG. 79, the SLC region is switched to the MLC region based onwear-out rate information. Accordingly, effects similar to those of theexample shown in FIG. 79 are gained.

In FIGS. 79 and 80, processing to switch the SLC region to the MLCregion when the write wear-out rate of the SLC region exceeds the SLCthreshold is described, but processing to switch the MLC region to theSLC region when the write wear-out rate of the MLC region exceeds theMLC threshold is similar.

Normally, when compared with the SLC region, the MLC region has a lowerwritable upper limit count set thereto. Thus, even if the write wear-outrate of the MLC region exceeds the MLC threshold, a higher writableupper limit count can be set by switching the MLC region to the SLCregion. If, for example, the writable upper limit count of the MLCregion is 1000 and the writable upper limit count of the SLC region is10000, the MLC threshold is reached with 80% of the wear-out rate in theMLC region. By switching the MLC region to the SLC region, for example,the region can be written into as an SLC region 2000 times more. Byusing the SLC region, like the MLC region, as a memory region into whichdata with a low access frequency is written, the life of the memoryregion can further be prolonged.

FIG. 81 is a state transition diagram showing a first example ofswitching control of memory regions by the switching control unit D36according to the present embodiment. Incidentally, the processingdescribed as steps OA1 to OA5 in FIG. 81 may be changed in order withinthe range in which switching of the SLC region and the MLC region,movement of data, and information updates are implemented normally.

In step OA1, a memory region MA of the nonvolatile semiconductor memoryis an SLC region and memory regions MB, MC, MD of the nonvolatilesemiconductor memory are MLC regions. The memory regions MA, MB, MCstore data Da, Db, Dc respectively. The memory region MD is a saveregion.

In step OA1, it is assumed that the write wear-out rate of the memoryregion MA exceeds the SLC threshold.

Then, in step OA2, the switching control unit D36 selects one of thememory regions MB, MC (the memory region MB in the example of FIG. 81)in the MLC region and moves the data Db in the selected memory region MBto the save memory region MD. The selection of the memory regions MB, MCin the MLC region may be made by preferentially selecting a memoryregion in the MLC region in which no data is stored, preferentiallyselecting a memory region in the MLC region in which data with lowimportance is stored based on the coloring table 14, or preferentiallyselecting a memory region in the MLC region with a low write wear-outrate, read wear-out rate, or erasure wear-out rate. This selection maybe modified in various ways.

As the movement destination (save destination) of the data Db of thememory region MB, data with a high access frequency of data contained inthe data Db may be saved in the SLC region by referencing the colortable 14 and data with a low access frequency of data contained in thedata Db may be saved in the MLC region.

Next, in step OA3, the switching control unit D36 switches the selectedmemory MB in the MLC to the SLC and changes SLC/MLC region informationof the memory region MB.

Next, in step OA4, the switching control unit D36 moves the data Da ofthe memory region MA in the SLC to be switched to the memory region MBnewly switched to the SLC.

Then, in step OA5, the switching control unit D36 switches the memoryregion MA in the SLC to be switched to the MLC and changes SLC/MLCregion information of the memory region MA.

In each of the above steps, with the movement of data, the addressconversion information 13 is updated to associate the physical addressof the movement destination of data with the logical address of thedata. If data writing, reading, or erasure occurs with the movement ofdata, the memory usage information 11 is updated.

FIG. 82 is a state transition diagram showing a second example ofswitching control of memory regions by the switching control unit D36according to the present embodiment. Incidentally, the processingdescribed as steps OB1 to 085 in FIG. 82 may be changed in order withinthe range in which switching of the SLC and the MLC, movement of data,and information updates are implemented normally.

In step OB1, the memory region MA of the nonvolatile semiconductormemory is an SLC and the memory regions MB, MC, MD of the nonvolatilesemiconductor memory are MLCs. The memory regions MA, MB, MC store thedata Da, Db, Dc respectively. The memory region MD is a save region.

In step OB1, it is assumed that the write wear-out rate of the memoryregion MA exceeds the SLC threshold.

Then, in step OB2, the switching control unit D36 moves the data Da inthe memory region MA to the save memory region MD.

Next, in step OB3, the switching control unit D36 selects one of thememory regions MB, MC (the memory region MB in the example of FIG. 82)in the MLC and moves the data Db in the selected memory region MB to thesave memory region MD.

Next, in step OB4, the switching control unit D36 switches the memoryregion MA in the SLC to the MLC and the memory region MB in the MLC tothe SLC. Further, the switching control unit D36 changes SLC/MLC regioninformation of the memory regions MA, MB.

Then, in step OB5, the switching control unit D36 moves the data Da inthe save memory region MD to the memory region MB switched to the SLCand the data Db in the save memory region MD to the memory region MAswitched to the MLC.

In each of the above steps, with the movement of data, the addressconversion information 13 is updated to associate the physical addressof the movement destination of data with the logical address of thedata. If data writing, reading, or erasure occurs with the movement ofdata, the memory usage information 11 is updated.

As described above, after the SLC region being changed to the MLCregion, as shown in the first embodiment, the coloring table 17 isreferenced to write (arrange) data with a high access frequency into theSLC region and write (arrange) data with a low access frequency into theMLC region.

In the present embodiment described above, the SLC region candynamically be switched to the MLC region in accordance with the usagestate of the nonvolatile semiconductor memories 9, 10 and also the MLCregion can dynamically be switched to the SLC region. By switching theSLC region to the MLC region, the SLC region with a high write wear-outrate can be used as the MLC region. Further, by switching the MLC regionto the SLC region, the MLC region with a low write wear-out rate can beused as the SLC region. Accordingly, the life of the nonvolatilesemiconductor memories 9, 10 can be prolonged so that the nonvolatilesemiconductor memories 9, 10 can be used efficiently.

Ninth Embodiment

The present embodiment is a modification of the first embodiment. In thepresent embodiment, a memory expansion device that expands the addressspace used by the processors 3 a, 3 b, 3 c will be described.

FIG. 83 is a block diagram showing an example of the relationshipbetween the memory expansion device according to the present embodimentand the address space. In FIG. 83, the processor 3 b of the processors 3a, 3 b, 3 c will representatively be described, but the other processors3 a, 3 c can also be described in the same manner.

The memory management device 1 described in the first embodiment makesan address conversion between a logical address space E32 of memory anda physical address space E33 of memory and also determines the writingdestination of data.

The physical address space E33 of memory contains the physical addressspace of the mixed main memory 2. The physical address space E33 ofmemory may further contain the physical address space of another memory.

The logical address space E32 of memory corresponds to a processorphysical address space E34 for the processor 3 b. In the processorphysical address space E34, for example, data management based on filesystems E34 a, E34 b is realized.

The processor 3 b includes a memory management device E35. Incidentally,the processor 3 b and the memory management device E35 may be separatestructures.

The processor 3B executes a plurality of processes Pc1 to Pcn. In theplurality of processes Pc1 to Pcn, processor logical address spaces PLA1to PLAn are used respectively. If, for example, the processor 3 b is aCPU (Central Processing Unit), the processor logical address spaces PLA1to PLAn are CPU logical address spaces.

The processor logical address spaces PLA1 to PLAn have memory windowsMW1 to MWn respectively. Data in a portion of the processor physicaladdress space E34 is mapped (that is, copied or mapped) to the memorywindows MW1 to MWn.

Accordingly, the processor 3 b can access data in the memory windows MW1to MWn in parallel in the plurality of processes Pc1 to Pcn so as to beable to execute the plurality of processes Pc1 to Pcn at high speed.

Even if the size of the address space that can be used by the processor3 b is limited, the processor 3 b virtually can use a wide address spaceby using the memory windows MW1 to MWn.

If data that is not mapped to the memory windows MW1 to MWn is neededfor the processes Pc1 to Pcn, the processor 3 b updates data in thememory windows MW1 to MWn and the needed data is thereby mapped newly tothe memory windows MW1 to MWn.

The processor 3 b can access the processor physical address space E34via the memory windows MW1 to MWn.

The memory management device E35 according to the present embodiment hasa configuration similar to that of the memory management device 1described in the first embodiment. In the present embodiment, the memorymanagement device E35 further realizes a function as an MMU of theprocessor 3 b, but the memory management device E35 and the MMU of theprocessor 3 b may be separate structures.

A major feature of the memory management device E35 according to thepresent embodiment is that address conversions and writing destinationdecisions of data are made between the processor logical address spacesPLA1 to PLAn and the processor physical address space E34.

The information storage unit 17 of the memory management device E35stores memory usage information E36, memory specific information E37, acoloring table E38, and address conversion information E39.

The processing unit 15 of the memory management device E35 references orupdates the memory usage information E36, the memory specificinformation E37, the coloring table E38, and the address conversioninformation E39 in the information storage unit 17 while using theworking memory 16 to perform processing similar to the processingdescribed in the first embodiment.

The memory usage information E36 contains, for example, the writingoccurrence count and the reading occurrence count of each address regionof the processor physical address space E34 and the erasure count ofeach block region.

The memory usage information E36 indicating the usage state of eachaddress region of the processor physical address space E34 can becalculated based on, for example, the memory usage information 11 andthe address conversion information 13 managed by the memory managementdevice 1.

The memory specific information 12 contains, for example, the memorytype of each address region of the processor physical address space E34(for example, whether to correspond to the volatile semiconductor memory8, the nonvolatile semiconductor memory 9 of SLC, or the nonvolatilesemiconductor memory 10 of MLC), the memory size of the volatilesemiconductor memory 8, the memory size of the nonvolatile semiconductormemories 9, 10, the page size and block size of the nonvolatilesemiconductor memories 9, 10, and the accessible upper limit count (thewritable upper limit count, readable upper limit count, and erasableupper limit count) of each address region.

The memory specific information E37 indicating specific information ofeach address region of the processor physical address space E34 can becalculated based on, for example, the memory specific information 12 andthe address conversion information 13 managed by the memory managementdevice 1.

The coloring table E38 associates a processor logical address withcoloring information of data indicated by the processor logical address.

The address conversion information E39 is information associatingprocessor logical addresses with processor physical addresses. If thememory windows MW1 to MWn are updated, the address conversioninformation E39 is updated so as to represent a state after the update.

As described in the first embodiment, the processing unit 15 makesaddress conversions and writing destination decisions of data betweenthe processor logical address spaces PLAT to PLAn and the processorphysical address space E34 based on the memory usage information E36,the memory specific information E37, the coloring table E38, and theaddress conversion information E39.

More specifically, for example, the processing unit 15 exercises controlso that no write-back processing from the memory windows MW1 to MWn tothe processor physical address space E34 is performed on read-only datawhose writing frequency of data is 0.

If, for example, the data is of the type to be written and read and thevalue in the memory windows MW1 to MWn and the value in the processorphysical address space E34 are different (dirty data), the processingunit 15 writes back the value in the memory windows MW1 to MWn into theprocessor physical address space E34.

If, for example, the data is of the type (temporary) to be usedtemporarily, the processing unit 15 does not write back from the memorywindows MW1 to MWn into the processor physical address space E34 even ifthe data is dirty data.

For example, as described in the first embodiment, the processing unit15 allocates data to the volatile semiconductor memory 8 and thenonvolatile semiconductor memories 9, 10 based on the static writingfrequency SW_color, the static reading frequency SR_color, the staticerase frequency SE_color, the dynamic writing frequency DW_color, thedynamic reading frequency DR_color, the dynamic erase frequencyDE_color, and the data type.

FIG. 84 is a flow chart showing an example of the write operation by theprocessor 3 b and the memory management device E35 according to thepresent embodiment. In FIG. 84, an example of processing in which datawriting to the memory windows MW1 to MWn occurs and then changes ofprocessor physical address regions allocated to the memory windows MW1to MWn occur is shown.

In step EM1, the memory management device E35 initially allocates one ofprocessor physical address regions to the memory windows MW1 to MWn togenerate the address conversion information E39. At this point, theprocessor physical address region allocated to the memory windows MW1 toMWn corresponds to a memory region in the volatile semiconductor memory8, a memory region in the nonvolatile semiconductor memory 9 of SLC, ora memory region in the nonvolatile semiconductor memory 10 of MLC.

In step EM2, the processor 3 b writes data into the memory windows MW1to MWn. At the same time, the memory management device E35 updatescoloring information (for example, the writing count DWC_color, thedynamic writing frequency DW_color and the like) of the write targetdata.

In step EM3, if the processor 3 b writes data in the memory windows MW1to MWn into the processor physical address space E34, the memorymanagement device E35 determines the writing destination of the writetarget data into the processor physical address space E34 based on thememory usage information E36, the memory specific information E37, thecoloring table E38, and the address conversion information E39 and alsoupdates the memory usage information E36 and the address conversioninformation E39. Further, the memory management device E35 writes thewrite target data into the determined processor physical address region.

For example, the memory management device E35 determines, among a memoryregion of the volatile semiconductor memory 8, a memory region of thenonvolatile semiconductor memory 9 of SLC, and a memory region of thenonvolatile semiconductor memory 10 of MLC, the memory region into whichthe write target data should be written.

In step EM4, the processor 3 b causes access to data in anotherprocessor physical address region not allocated to the memory windowsMW1 to MWn.

In step EM5, the memory management device E35 changes the allocation ofthe processor physical address region to the memory windows MW1 to MWnand updates the address conversion information E39. The allocation ofthe processor physical address region to the memory windows MW1 to MWnis changed by, for example, a system call of the operating system 27. Inthe memory management device E35, page addresses are changed. Actually,entries of a processor page table are changed.

In this case, the memory management device E35 writes back data in thememory windows MW1 to MWn before the change to update coloringinformation of the data and the memory usage information E36.

In step EM6, the processor 3 b uses data stored in the memory windowsMW1 to MWn after the change.

In the present embodiment, even if the processor logical address spacesPLA1 to PLAn of the processor 3 b are small, the processor physicaladdress space E34 larger than the processor logical address spaces PLA1to PLAn can be used so that the processor physical address space E34 ofthe processor 3 b can be expanded.

In the present embodiment, data can efficiently be mapped between thememory windows MW1 to MWn and the processor physical address space E34by using coloring information.

Incidentally, in the present embodiment, the writing destination of datainto the processor physical address space E34 is determined based on thememory usage information E36, the memory specific information E37, andcoloring information of the coloring table E38. However, the writingdestination of data into the processor physical address space E34 may bedetermined by using, for example, at least one of the memory usageinformation E36, the memory specific information E37, and the coloringtable E38.

In the present embodiment, the processor logical address spaces PLA toPLn are formed for each of the plurality of processes Pc1 to Pcn and thememory windows MW1 to MWn are used for each. Accordingly, an operationsuch as accessing the mixed main memory 2 and the like in parallel isperformed so that the plurality of processes Pc1 to Pcn can be executedat high speed.

Tenth Embodiment

The present embodiment is an information processing device (serverdevice) that shares coloring information used by the memory managementdevice 1 in the first embodiment and sends the shared coloringinformation to the information processing device 100.

When new data is generated by the processes 6 a, 6 b, 6 c being executedby the processors 3 a, 3 b, 3 c in the information processing device 100respectively as described above, the operating system 27 generatesstatic color information based on the type of the newly generated datato give the static color information to the newly generated data. If thedata should be written into the nonvolatile semiconductor memories 9,10, the memory management device 1 can prolong the life of thenonvolatile semiconductor memories 9, 10 by referencing static colorinformation of the data to determine the write target memory region andthe like. Thus, the life of the nonvolatile semiconductor memories 9, 10can be made still longer by optimizing coloring information includingstatic color information.

In the present embodiment, a system that shares profile informationreferenced when the operating system 27 generates static colorinformation will be described. By sharing profile information,optimization of coloring information is realized. The profileinformation will be described later.

FIG. 85 is a diagram showing an example of the configuration of aninformation processing device and a network system according to thepresent embodiment.

A network system K32 has a configuration in which an informationprocessing device K33, a profile generation terminal K34, and userterminals 100A, 100B are communicably connected via a network K35.

The network K35 is, for example, a variety of communication media suchas the Internet and a LAN (Local Area Network) and may be a wire networkor a wireless network.

The configuration of the profile generation terminal K34 will bedescribed. The profile generation terminal K34 is, for example, aterminal of a program developer or a maker. The profile generationterminal K34 includes a setting unit K34 a, a storage device K34 b, anda communication unit K34 c.

The setting unit K34 a generates profile information K36 based on, forexample, a setting operation of a program developer or the like andstores the profile information K36 in the storage device K34 b.

The storage device K34 b stores the profile information K36 generated bythe setting unit K34 a.

The communication unit K34 c sends the profile information K36 stored inthe storage device K34 b to the information processing device K33 viathe network K35.

The configuration of the user terminals 100A, 100B will be described.The user terminals 100A, 100B correspond to the information processingdevice 100 in the first embodiment and include the memory managementdevice 1 and the mixed main memory 2. The coloring table 17 is stored inthe information storage unit 17 of the memory management device 1 andthe mixed main memory 2 included in the user terminals 100A, 100B.

The user terminals 100A, 100B generate profile information K37, K38automatically or according to user's instructions respectively. Detailsof generation of the profile information will be described later. Theuser terminals 100A, 100B send the profile information K37, K38 to theinformation processing device K33 via the network K35 respectively.

Further, the user terminals 100A, 100B download (receive) profileinformation from the information processing device K33 automatically oraccording to user's instructions. The operating system 27 of the userterminals 100A, 100B references the downloaded profile information whengenerating coloring information for data. The operating system 27 of theuser terminals 100A, 100B generate static color information for databased on profile information and store the static color information inthe coloring table 14.

The configuration of the information processing device K33 will bedescribed. The information processing device K33 includes acommunication unit K33 a, a profile information management unit K33 b,and a storage device K33 c. The profile information management unit K33may be realized by hardware or cooperation of software and hardware suchas a processor.

The communication unit K33 a sends and receives the profile informationK36 to K38 between the profile generation terminal K34 and the userterminals 100A, 100B.

The profile information management unit K33 b stores profile informationreceived via the communication unit K33 a in the storage device K33 c.The profile information management unit K33 b also sends profileinformation to the user terminals 100A, 100B and the profile generationterminal K34 via the communication unit K33 a.

The storage device K33 c stores profile information. Further, thestorage device K33 c stores service data K40. The service data K40 willbe described later.

Next, the profile information will be described. The profile informationis, as described above, information referenced by the operating system27 in the user terminals 100A, 100B when static color information isgiven (generated) to data.

The profile information is information associating, for example, dataidentification information, coloring information, and generatoridentification information.

The data identification information corresponds to, for example, thedata format of FIGS. 9 and 10 in the first embodiment. As the dataidentification information, identification information of a file such asthe name of a file and the extension of a file or information of theposition (for example, a directory) where data is arranged in a filesystem is used.

The coloring information contains the static color information describedabove. The static color information is a value set for each piece of thedata identification information and contains, for example, like in FIGS.9 and 10 in the first embodiment, the static writing frequency SW_color,the static reading frequency SR_color, and the data life SL_color.

The generator identification information is information to identify thegenerator of the profile information. The generator identificationinformation is additional information and is added if necessary.

Next, the generation of profile information will be described.

The user terminals 100A, 100B hold data identification information andcoloring information for the data identification information shown inFIGS. 9 and 10. The user terminals 100A, 100B generate profileinformation based on the held data identification information andcoloring information.

The user terminals 100A, 100B may also generate profile information fromthe coloring table 14 managed by the memory management device 1. Asdescribed above, the coloring table 14 is managed by the index generatedbased on the logical address specifying data and coloring information ofthe data in units of entries. The user terminals 100A, 100B identifydata specified by the logical address from the index to extract dataidentification information of the data. Further, the user terminals100A, 100B calculate static color information and dynamic colorinformation (for example, the dynamic writing frequency DW_color and thedynamic reading frequency DR_color) of the data. Further, if necessary,the user terminals 100A, 100B change the dynamic color information tothe data format similar to that of the static color information. While,as described above, the static color information is in the data formatlike SW_color=5, the dynamic color information is an actual accessfrequency to data and using, for example, a temporal average value ofaccess frequency can be considered. A conversion to the data format likeDW_color=5 is made in accordance with the magnitude of the accessfrequency of the dynamic color information or the temporal average valueof the access frequency. Accordingly, data identification information,and static color information and dynamic color information for the dataidentification information are determined. The user terminals 100A, 100Bgenerate profile information based on coloring information containingthe static color information and dynamic color information, dataidentification information, and generator identification information.

By generating profile information based on coloring informationcontaining dynamic color information in this manner, the actual accessfrequency to data can be provided to the user terminals 100A, 100B asprofile information. Accordingly, coloring information given to data bythe operating system 27 can be optimized.

For example, a software vendor that has developed a new application mayregister the profile information K36 about a file dedicated to the newapplication with the information processing device K33 by using theprofile generation terminal K34.

Next, the service data K40 will be described. The service data K40contains explanatory data of various kinds of the profile informationK36 to K38 stored in the storage device K33 c and various kinds ofadvertising data.

The service data K40 is sent from the information management unit K33 tothe user terminals 100A, 100B. The user terminals 100A, 100B display theservice data K40 by using, for example, a browser.

If, for example, the same data identification information is containedin a plurality of pieces of profile information stored in the storagedevice K33 c, the user can determine the profile information to bedownloaded by referencing the explanatory data of the service data K40.

By including, for example, advertising data of profile information,advertising data of information devices, and advertising data ofnonvolatile semiconductor memories in the service data K40, specificproducts can be recommended to the user who considers downloadingprofile information, purchasing a new information device, or purchasinga new nonvolatile semiconductor memory.

For example, the profile information management unit K33 b may apply astatistical method to the profile information K36 to K38 stored in thestorage device K33 c to send resultant profile information to the userterminals 100A, 100B. As the statistical method, for example, a methodof calculating an average value or determining a median for coloringinformation associated with the same data identification information.For example, the profile information management unit K33 b generatesprofile information containing an average value or median of the staticwriting frequency SW_color, an average value or median of the staticreading frequency SR_color, an average value or median of the data lifeSL_color, an average value or median of the dynamic writing frequencyDW_color, an average value or median of the dynamic reading frequencyDR_color for a plurality of pieces of coloring information associatedwith the same data identification information and sends the generatedprofile information to the user terminals 100A, 100B.

The profile information management unit K33 b counts the number ofdownloads of the profile information K36 to K38 by a browser of the userterminals 100A, 100B. The profile information management unit K33 bcalculates a compensation charge for the generator of each piece ofprofile information K36 to K38 by multiplying the download count of eachpiece of profile information K36 to K38 by a download charge perdownload of the profile information K36 to K38. Then, the profileinformation management unit K33 b generates compensation information inwhich compensation charges are assigned for generator identificationinformation of each piece of profile information K36 to K38 and storesthe compensation information in the storage device K33 c.

Further, the profile information management unit K33 b generates usagecharge information in which a usage charge per download of profileinformation is assigned for identification information (for example, theuser ID) that identifies the download request source in response to adownload request from the user terminals 100A, 100B and stores the usagecharge information in the storage device K33 c.

FIG. 86 is a flow chart showing an example of processing of the profileinformation management unit K33 b according to the present embodiment.

In step C1, the profile information management unit K33 b determinesfrom which of the profile generation terminal K34 and the user terminals100A, 100B one piece of the profile information K36 to K38 is received.

If no profile information K36 to K38 is received, the processingproceeds to step C3.

If one piece of the profile information K36 to K38 is received, in stepC2, the profile information management unit K33 b stores the receivedprofile information in the storage device K33 c.

In step C3, the profile information management unit K33 b determinesfrom which of the user terminals 100A, 100B a download request isreceived.

If no download request is received, the processing proceeds to step C6.

If a download request is received, in step C4, the profile informationmanagement unit K33 b reads profile information corresponding to thereceived download request from the storage device K33 c.

In step C5, the profile information management unit K33 b sends the readprofile Information to the user terminal of the download request source.

In step C6, the profile information management unit K33 b determineswhether the processing has ended. If the processing has not ended, theprocessing returns to step C1.

FIG. 87 b is a flow chart showing an example of upload processing of theprofile information K37 by the user terminal 100A according to thepresent embodiment. Upload processing by the user terminal 100B isalmost the same as in FIG. 87.

In step UL1, the user terminal 100A generates the profile informationK37 by combining data identification information for data, coloringinformation in the coloring table 14 associated with the data, andgenerator identification information, for example, automatically oraccording to user's instructions.

In step UL2, the user terminal 100A sends the generated profileinformation K37 to the information management unit K33 via the networkK35.

FIG. 88 is a flow chart showing an example of download processing ofprofile information by the user terminal 100A according to the presentembodiment. Download processing by the user terminal 100B is almost thesame as in FIG. 88 and thus, the description thereof is omitted.

In step DL1, the user terminal 100A sends a download request containingdata identification information to the information management unit K33via the network K35, for example, automatically or according to user'sinstructions.

In step DL2, the user terminal 100A receives profile information fromthe information management unit K33 via the network K35 as a response tothe download request.

In step DL3, the operating system 27 of the user terminal 100A storesstatic color information contained in the received profile informationfor data corresponding to the data identification information of thereceived profile information in the coloring table 14.

In step DL4, the memory management device 1 of the user terminal 100Adetermines whether dynamic color information is contained in thereceived profile information.

If no dynamic color information is contained in the received profileinformation, the processing ends.

If dynamic color information is contained in the received profileinformation, in step DL5, the memory management device 1 stores staticcolor information contained in the received profile information for datacorresponding to the data identification information of the receivedprofile information in the coloring table 14.

In the present embodiment described above, coloring information used bythe memory management device 1 is generated by many such as makers andusers and the generated coloring information is shared.

In the present embodiment, charges can be paid to the generator ofcoloring information in accordance with the number of times the coloringinformation is browsed or downloaded.

In the present embodiment, the operator of the information managementunit K33 can collect many pieces of coloring information and speedilyprovide various services concerning coloring information.

By using the information management unit K33 according to the presentembodiment, coloring information can be shared, the development of thememory management device 1 and the mixed main memory 2 can be hastened,and the memory management device 1 and the mixed main memory 2 can bepopularized.

Eleventh Embodiment

The present embodiment is a modification of the first embodiment. In thepresent embodiment, a memory management device that accesses a memoryconnected via a network will be described.

FIG. 89 is block diagram showing an example of a network systemaccording to the present embodiment.

A network system N37 includes an information processing device N37A andan information processing device N37B. The information processing deviceN37A and the information processing device N37B are connected via anetwork N38. The information processing device N37A and the informationprocessing device N37B have the same function and thus, the informationprocessing device N37A will be described in detail below. Incidentally,the network system N37 may include three information processing devicesor more.

The information processing device N37A includes a processor 3A, a memorymanagement device N32A, a volatile semiconductor memory 8A, anonvolatile semiconductor memory 9A, and a network interface deviceN39A.

The processor 3A is connected to the volatile semiconductor memory 8A,the nonvolatile semiconductor memory 9A, and the network interfacedevice N39A via the memory management device N32A.

The processor 3A may include an internal memory cache, but a descriptionthereof is omitted in FIG. 89. The information processing device N37Amay include a plurality of processors 3A.

The volatile semiconductor memory 8A is similar to the volatilesemiconductor memory 8 in the first embodiment. The nonvolatilesemiconductor memory 9A is similar to the nonvolatile semiconductormemory 9 or the nonvolatile semiconductor memory 10 in the firstembodiment.

In the present embodiment, the volatile semiconductor memory 8A and thenonvolatile semiconductor memory 9A are used as the main memory of theinformation processing device N37A. However, the volatile semiconductormemory 8A and the nonvolatile semiconductor memory 9A function as cachememories in the information processing device N37A by storing data witha high access frequency or data whose importance is high for theinformation processing device N37A of data in the other informationprocessing device N37B. In this case, the volatile semiconductor memory8A is used as the primary cache memory in the information processingdevice N37A and the nonvolatile semiconductor memory 9A is used as thesecondary cache memory in the information processing device N37A.

The network interface device N39A sends/receives network logicaladdresses or data to/from the network interface device N39A of the otherinformation processing device N37B via the network N38.

The memory management device N32A according to the present embodimentwill be described. FIG. 90 is a block diagram showing an example of theconfiguration of the memory management device N32A according to thepresent embodiment.

A processing unit N33A of the memory management device N32A includes, inaddition to the address management unit 18, the reading management unit19, the writing management unit 20, the coloring information managementunit 21, the memory usage information management unit 22, and therelocation unit 23, a network address conversion unit N34 and acommunication unit N35.

The network address conversion unit N34 converts a logical address ofshort address length used by the processor 3A (hereinafter, referred toas a “processor logical address”) into a logical address of long addresslength used by a plurality of information processing devices connectedby a network (hereinafter, referred to as a “network logical address”).In the address conversion, for example, a hash function is used.Incidentally, the processor logical address is a pointer stored in aregister.

The working memory 16 has an address length conversion table AT storedtherein. The network address conversion unit N34 references the addresslength conversion table AT to convert a processor logical address into anetwork logical address.

Incidentally, the address length conversion table AT is stored in theworking memory 16, but may also be stored in the information storageunit 17.

The communication unit N35 sends and receives network logical addressesand data specified by network logical addresses via the network N38 byusing the network interface device N39A.

In the present embodiment, the memory usage information 11 indicates theusage state of the whole network system N37 (in the example of FIG. 90,the memory usage information 11 includes the volatile semiconductormemory 8A, the nonvolatile semiconductor memory 9A, a volatilesemiconductor memory 8B, a nonvolatile semiconductor memory 9B).

Similarly, the memory specific information 12 indicates specificinformation of memory regions of the whole network system N37.

The address conversion information 13 indicates the relationship betweennetwork logical addresses and physical addresses used by the wholenetwork system N37.

The coloring table 14 contains coloring Information of each piece ofdata in the whole network system N37.

In the network system N37, unique addresses are attached to all data. Ifa common network logical address space is used throughout the networksystem N37, the number of bits of needed addresses increases like 128bits. In the network system N37, however, the processors 3A, 3B areassumed to have 32-bit or 64-bit registers. In this case, it isnecessary to convert a processor logical address of the number of bitsof the register into the number of bits of a network logical address.The conversion processing is performed by the network address conversionunit N34 included in the memory management devices N32A, N32B.

Data reading by the network system N37 via the network N38 will bedescribed.

The memory management device N32A receives a processor logical addressfrom the processor 3A and converts the processor logical address into anetwork logical address. Then, if data corresponding to the networklogical address is stored in none of the memories (in FIG. 90, thevolatile semiconductor memory 8A and the nonvolatile semiconductormemory 9A) of the information processing device N37A, the memorymanagement device N32A sends the network logical address to the otherinformation processing device N37B via the network interface device N39Aand the network N38.

The memory management device N32B of the information processing deviceN37B receives data corresponding to the network logical address from theinformation processing device N37A via the network N38 and a networkinterface device N39B.

If the received network logical address is stored in the memory (in FIG.90, the volatile semiconductor memory 8B or the nonvolatilesemiconductor memory 9B) of the information processing device N37B, thememory management device N32B converts the network logical address intoa physical address based on the address conversion information 13 toread data.

The memory management device N32B sends the read data to the informationprocessing device N37A via the network interface device N39A and thenetwork N38.

The memory management device N32A of the information processing deviceN37A receives the read data from the information processing device N37Bvia the network N38 and the network interface device N39A.

The memory management device N32A returns the read data to the processor3A.

The memory management device N32A references the coloring table 14 and,if the access frequency or the importance of the read data is equal toor more than a predetermined value, writes the data into the volatilesemiconductor memory 8B or the nonvolatile semiconductor memory 9B andupdates the address conversion information 13. The writing destinationfor the writing is determined by the same method as in the firstembodiment.

Data writing by the network system N37 via the network N38 will bedescribed.

The memory management device N32A receives a processor logical addressand write target data from the processor 3A and converts the processorlogical address into a network logical address. Then, if the networklogical address indicates the other information processing device N37B,the memory management device N32A sends the network logical address andthe write target data to the other information processing device N37Bvia the network interface device N39A and the network N38.

The memory management device N32B of the information processing deviceN37B receives the network logical address and the write target data fromthe information processing device N37A via the network N38 and thenetwork interface device N39B.

The memory management device N32B converts the network logical addressinto a physical address based on the address conversion information 13and writes the write target data into the memory region indicated by thephysical address.

Copying of the data D1 in the network system N37 shown in FIG. 89 willbe described.

The memory management device N32A of the information processing deviceN37A manages the memory usage information 11 and the memory specificinformation 12 for the volatile semiconductor memory 8A and thenonvolatile semiconductor memory 9A and further, the volatilesemiconductor memory 8B and the nonvolatile semiconductor memory 9B.

Further, the memory management device N32A manages coloring informationof each piece of data stored in the volatile semiconductor memory 8A andthe nonvolatile semiconductor memory 9A and further, the volatilesemiconductor memory 8B and the nonvolatile semiconductor memory 9B bythe coloring table 14.

The memory management device N32A determines the writing destinationfor, in addition to the volatile semiconductor memory 8A and thenonvolatile semiconductor memory 9A, the volatile semiconductor memory8B and the nonvolatile semiconductor memory 9B based on the memory usageinformation 11, the memory specific information 12, and the coloringtable 14 so that the life of the nonvolatile semiconductor memories 9A,9B are prolonged.

The memory management device N32A of the information processing deviceN37A copies the data D1 of the main body with a high access frequencyfrom the information processing device N37A to the other informationprocessing device N37B to the volatile semiconductor memory 8A or thenonvolatile semiconductor memory 9A of the information processing deviceN37A to store the data as data D1 c. For example, the memory managementdevice N32A references the coloring table 14 to store the data D1 storedin the other information processing device N37B and whose accessfrequency is equal to or more than a predetermined level as the data D1c copied to the volatile semiconductor memory 8A or the nonvolatilesemiconductor memory 9A of the information processing device N37A.

If the access frequency to the data D1 c copied to the informationprocessing device N37A is larger than the access frequency to the dataD1 in the information processing device N37B over the predeterminedlevel, the memory management devices N32A, N32B manage the data D1 ccopied to the information processing device N37A as the main body.

Further, if a write operation to the copied data D1 c occurs in theinformation processing device N37A, the memory management devices N32A,N32B manage the data D1 c in the information processing device N37A asthe main body.

Thus, if the data D1 c copied to the information processing device N37Ais managed as the main body, the data D1 in the information processingdevice N37B is maintained as it is and mutually different addresses (ID)may be allocated to the data D1, D1 c. A different address may beallocated to the original data D1 or to the copied data D1 c.

If the data D1 c is managed as the main body, the original data D1 maybe erased.

The memory management devices N32A, N32B manage the data D1, D1 c sothat if, for example, a write operation to the data D1 c used as a cacheoccurs, the data D1 as the main body is updated to avoid an occurrenceof collision of the data D1, D1 c.

FIG. 91 is a block diagram showing a first relationship between theprocessor logical address and the network logical address according tothe present embodiment.

For example, an upper address P1 u of a processor address Pr1 is a32-bit address and a lower address P1 d thereof is a 32-bit address.

For example, a combination of an upper address N1 u and a middle addressN1 m of a network logical address N1 is a 128-bit address and a loweraddress N1 d thereof is a 32-bit address.

The upper address N1 u of the network logical address N1 is assumed toindicate, for example, an operator and the middle address N1 m of thenetwork logical address N1 is assumed to indicate, for example, aprocessor specific value. The upper address N1 u and the middle addressN1 m of the network logical address N1 are network related addressesand, for example, IP addresses or IPv4.

The combination of the upper address N1 u and the middle address N1 m ofthe network logical address N1 is converted by a hash function N40. Theupper address P1 u of the processor logical address Pr1 having a smallernumber of bits than the upper address N1 u and the middle address N1 mof the network logical address N1 is determined by the conversion. Theupper address P1 u of the processor logical address Pr1 is used as a keyof the conversion from the processor logical address Pr1 into thenetwork logical address N1.

The lower address N1 d of the network logical address N1 u is used asthe lower address P1 d of the processor logical address Pr1 as it is.

The upper address N1 u and the middle address N1 m of the networklogical address N1 are stored in the position indicated by the upperaddress P1 u of the processor logical address Pr1 in an address lengthconversion table AT1.

When converting the processor logical address Pr1 into the networklogical address N1, the network address conversion unit N34 referencesthe position indicated by the upper address P1 u of the processorlogical address Pr1 in the address length conversion table AT1 todetermine the upper address N1 u and the middle address N1 m of thenetwork logical address N1 stored in this position.

Then, the network address conversion unit N34 determines the networklogical address N1 by combining the upper address N1 u and the middleaddress N1 m of the network logical address N1 determined above with thelower address P1 d of the processor logical address Pr1.

Each entry of the address length conversion table AT1 has an addresslength conversion flag indicating whether or not valid/invalid attachedthereto.

When registering an entry with the address length conversion table AT1,the network address conversion unit N34 references the address lengthconversion flag of the registration destination. If the address lengthconversion flag is invalid, the network address conversion unit N34makes an entry registration as it is. If the address length conversionflag is valid, the network address conversion unit N34 performsexception processing. Accordingly, duplicate registration can beprevented.

FIG. 92 is a block diagram showing a second relationship between aprocessor logical address Pr2 and a network logical address N2 accordingto the present embodiment.

A middle address N2 m of the network logical address N2 is used as anupper address P2 u of the processor logical address Pr2. The upperaddress P2 u of the processor logical address Pr2 is used as a key ofthe conversion from the processor logical address Pr2 into the networklogical address N2.

A lower address N2 d of the network logical address N2 is used as alower address P2 d of the processor logical address Pr2 as it is.

An upper address N2 u and the middle address N2 m of the network logicaladdress N2 are stored in the position indicated by the upper address P2u of the processor logical address Pr2 in an address length conversiontable AT2.

When converting the processor logical address Pr2 into the networklogical address N2, the network address conversion unit N34 referencesthe position indicated by the upper address P2 u of the processorlogical address Pr2 in the address length conversion table AT2 todetermine the upper address N2 u and the middle address N2 m of thenetwork logical address N2 stored in this position.

Then, the network address conversion unit N34 determines the networklogical address N2 by combining the upper address N2 u and the middleaddress N2 m of the network logical address N2 determined above with thelower address P2 d of the processor logical address Pr2.

FIG. 93 is a block diagram showing a third relationship between theprocessor logical address and the network logical address according tothe present embodiment.

A middle address N3 m and a lower address N3 d of a network logicaladdress N3 are used as an upper address P3 u and a lower address P3 d ofa processor logical address Pr3. The upper address P3 u of the processorlogical address Pr3 is used as a key of the conversion from theprocessor logical address Pr3 into the network logical address N3.

An upper address N3 u of the network logical address N3 is stored in theposition indicated by the upper address P3 u of the processor logicaladdress Pr3 in an address length conversion table AT3.

When converting the processor logical address Pr3 into the networklogical address N3, the network address conversion unit N34 referencesthe position indicated by the upper address P3 u of the processorlogical address Pr3 in the address length conversion table AT3 todetermine the upper address N3 u of the network logical address N3stored in this position.

Then, the network address conversion unit N34 determines the networklogical address N3 by combining the upper address N3 u of the networklogical address N3 determined above with the upper address P3 u and thelower address P3 d of the processor logical address Pr3.

FIG. 94 is a block diagram showing a fourth relationship between theprocessor logical address and the network logical address according tothe present embodiment.

The network address conversion unit N34 extracts a value at n-bitintervals from a combination of an upper address N4 u and a middleaddress N4 m of a network logical address N4 to set the extracted valueas an upper address P4 u of a processor logical address Pr4. The upperaddress P4 u of the processor logical address Pr4 having a smallernumber of bits than the upper address N4 u and the middle address N4 mof the network logical address N1 is determined by the conversion. Theupper address P4 u of the processor logical address Pr4 is used as a keyof the conversion from the processor logical address Pr4 into thenetwork logical address N4.

Other relationships between the network logical address N4 and theprocessor logical address Pr4 and the conversion from the processorlogical address Pr4 into the network logical address N4 are the same asthose in FIG. 91 and thus, the description thereof is omitted.

FIG. 95 is a block diagram showing a fifth relationship between theprocessor logical address and the network logical address according tothe present embodiment.

The network address conversion unit N34 sets the value of a remainderobtained by dividing a combination of an upper address N5 u and a middleaddress N5 m of the network logical address N5 by a value P (forexample, a prime number) as an upper address P5 u of a processor logicaladdress Pr5. The upper address P5 u of the processor logical address Pr5having a smaller number of bits than the upper address N5 u and themiddle address N5 m of the network logical address N5 is determined bythe conversion. The upper address P5 u of the processor logical addressPr5 is used as a key of the conversion from the processor logicaladdress Pr5 into the network logical address N5.

Other relationships between the network logical address N5 and theprocessor logical address Pr5 and the conversion from the processorlogical address Pr5 into the network logical address N5 are the same asthose in FIG. 91 and thus, the description thereof is omitted.

The network address conversion unit N34 may use, instead of a hashfunction 40, a conversion table to convert a portion of the networklogical addresses N1 to N5 into a portion of the processor logicaladdresses Pr1 to Pr5 to use the portion of the processor logicaladdresses Pr1 to Pr5 as keys to convert the address length.

The network address conversion unit N34 may also create a table thatregisters a portion or all of the network logical addresses N1 to N5 touse the table as a key used for conversion from the processor logicaladdresses Pr1 to Pr5 into the network logical addresses N1 to N5.According to this conversion method, each of the information processingdevices N37A, N37B may manage such a table. Preferably, the informationprocessing devices N37A, N37B connected to the network N38 are caused toshare a table so that each of the information processing devices N37A,N37B locally stores a copy of the table in a cache memory or the like.

In the above conversion, the lower addresses N1 d to N5 d of the networklogical addresses N1 to N5 and the lower addresses P1 d to P5 d of theprocessor logical addresses Pr1 to Pr5 are used without being converted,but the lower addresses N1 d to N5 d of the network logical addresses N1to N5 and the lower addresses P1 d to P5 d of the processor logicaladdresses Pr1 to Pr5 may be converted.

FIG. 96 is a block diagram showing an example of a virtual address spaceof the network system N37 according to the present embodiment.

In the present embodiment, unique network logical addresses areallocated to all data in the network system N37 and thus, a virtualaddress space N41 common to the information processing devices N37A,N37B can be formed.

FIG. 97 is a block diagram showing a first example of the configurationof a processor logical address and a network logical address accordingto the present embodiment.

A processor logical address N42 includes a conversion key and a fileaddress+offset.

The network address conversion unit N34 converts the processor logicaladdress N42 into a network logical address N43.

The network logical address N43 includes processor identificationinformation (for example, identification information of the operator andinformation processing device) and a file address+offset.

The memory management device N32A sends the network logical address N43to the memory management device N32B via the network N38. Then, thememory management device N32B reads data specified by the fileaddress+offset of the network logical address N43 and returns the datato the memory management device N32A.

FIG. 98 is a block diagram showing a second example of the configurationof a processor logical address and a network logical address accordingto the present embodiment.

A processor logical address N44 includes a conversion key and an offset.

The network address conversion unit N34 converts the processor logicaladdress N44 into a network logical address N45.

The network logical address N45 includes processor identificationinformation, a file address and an offset.

The memory management device N32A sends the network logical address N45to the memory management device N32B via the network N38. Then, thememory management device N32B reads data specified by the fileaddress+offset of the network logical address N45 and returns the datato the memory management device N32A.

FIG. 99 is a block diagram showing a third example of the configurationof a processor logical address and a network logical address accordingto the present embodiment.

A processor logical address N46 includes a conversion key and a fileaddress.

The network address conversion unit N34 converts the processor logicaladdress N46 into a network logical address N47.

The network logical address N47 includes processor identificationinformation and a file address.

The memory management device N32A sends the network logical address N47to the memory management device N32B via the network N38. Then, thememory management device N32B reads file data specified by the fileaddress of the network logical address N47 and returns the data to thememory management device N32A.

Technical significance of the address conversion as described above willbe described below.

For example, an 8-bit CPU (Central Processing Unit) is generally used asthe processor 3A. The 8-bit CPU includes 8-bit registers. The number ofbits of an address in a generally used 8-bit CPU is 16 bits.

For example, a 16-bit CPU includes 16-bit registers. The number of bitsof an address in a generally used 16-bit CPU is 20 bits.

Both numeric values and addresses are stored in a general register.Thus, it is desirable that the number of bits of a numeric value and thenumber of bits of an address match. However, as described above, thenumber of bits of a register and the number of bits of an address maynot match.

64-bit CPUs are currently in widespread use. 64-bit CPUs can providesufficient arithmetic precision. Thus, the need for the number of bitsof a register to exceed 64 bits is low. Moreover, from the viewpoint ofcarry processing of a CPU adder, including a register exceeding 64 bitsin a CPU is considered to be difficult.

In contrast, the need for the number of bits of an address to increaseis considered to be high. As an example thereof, Single Level Store(SLS) will be described.

In the SLS, virtual addresses are allocated to various storage devicesincluding secondary storage devices. In recent years, a local storagedevice that is not connected via a network has the capacity on the orderof Tbytes and thus, 32 bits are not sufficient and 64 bits aresufficient.

However, when a storage device like, for example, (NAS) used in anetwork environment is used or addresses are allocated to a large numberof storage devices connected to a network, it is necessary to increasethe size of the virtual address to, for example, 128 bits.

FIG. 100 is a diagram showing an example of calculation to estimate thenumber of bits of the address needed to access data stored in a largenumber of devices connected to a network.

If it is assumed, as shown in FIG. 100, that human beings worldwidestore a certain level of data, such data can be accessed by using 82-bitnetwork logical addresses.

Therefore, as described above, determining a network logical address fora network having a larger number of bits from a processor logicaladdress having the same number of bits as a register of the processors3A, 3B in the network system N37 is highly significant.

In the present embodiment, for example, addresses can be allocated toall data in a network system by adopting a 128-bit network logicaladdress.

In the present embodiment described above, addresses can be allocated toall data used in the network system N37.

In the present embodiment, basic memory management such as the addressconversion and writing destination decision and the memory access can beimplemented by a common method between the volatile semiconductor memory8A and the nonvolatile semiconductor memory 9A, and the volatilesemiconductor memory 8B and the nonvolatile semiconductor memory 9Bincluded in the network system N37. That is, each of the informationprocessing devices N37A, N37B according to the present embodiment doesnot have to distinguish between a memory included in the local deviceand a memory connected via the network N38 in management of the accessmethod, access count, access frequency and the like.

In the present embodiment, data with a high frequency of being accessedby the information processing devices N37A, N37B is stored in therespective device and thus, an access delay due totransmission/reception via the network N38 and an access failure causedby a network disconnection can be prevented.

In the present embodiment, the volatile semiconductor memory 8A and thenonvolatile semiconductor memory 9A, and the volatile semiconductormemory 8B and the nonvolatile semiconductor memory 9B in the networksystem N37 can be used as the main memory. Further, each of theinformation processing devices N37A, N37B according to the presentembodiment can use a memory in the local device as a cache memory tostore data stored in the other device.

In the present embodiment, addresses of the number of bits larger thanthe number of bits of registers of the processors 3A, 3B can be used sothat a wide memory space can be used.

In general, access that is not made via a network is reading/writingfrom/to a storage device and access that is made via a network is madeby socket communication. Reading/writing and socket communication usedifferent access methods. For example, a special access method using URLor the like is used for Web access via a network. In the presentembodiment, by contrast, access to a storage device is made based on anetwork logical address regardless of whether accessed via a network sothat the same access method is used.

In the present embodiment, the address length conversion flag isattached to the address length conversion tables AT, and AT1 to AT5,which can prevent duplicate registration.

Each element described in each of the above embodiments can freely becombined and divided. For example, any functional block shown in eachembodiment can appropriately be combined and divided. Also, for example,only steps of a portion of the flow chart shown in each embodiment canbe extracted and executed and any steps can appropriately be combinedand divided.

The present invention is not limited to the above embodiments andvarious modifications can be made in the stage of working withoutdeviating from the scope thereof. Further, the above embodiments containinventions of various stages and various inventions can be extracted byappropriately combining a plurality of disclosed constituent features.

1. A memory management device that controls writing into and readingfrom a main memory comprising a nonvolatile semiconductor memory and avolatile semiconductor memory in response to a writing request and areading request from a processor, the memory management devicecomprising: a coloring information storage unit that stores coloringinformation generated based on a data characteristic of write targetdata to be written into at least one of the nonvolatile semiconductormemory and the volatile semiconductor memory; and a writing managementunit that references the coloring information to determines a regioninto which the write target data is written from the nonvolatilesemiconductor memory and the volatile semiconductor memory.
 2. Thememory management device according to claim 1, wherein the coloringinformation comprises an access frequency estimated based on the datacharacteristic of the write target data.
 3. The memory management deviceaccording to claim 1, wherein the coloring information comprises a datalife estimated based on the data characteristic of the write targetdata.
 4. The memory management device according to claim 1, wherein thecoloring information comprises importance estimated based on the datacharacteristic of the write target data.
 5. The memory management deviceaccording to claim 1, wherein the coloring information further comprisesan access count to the write target data.
 6. The memory managementdevice according to claim 1, wherein the coloring information comprisesat least one of an access frequency, a data life, and importanceestimated based on the data characteristic of the write target data. 7.The memory management device according to claim 2, wherein thenonvolatile semiconductor memory comprises a first region and a secondregion, the writing management unit references the coloring informationto write the write target data of which the access frequency is highestimated based on the data characteristic into the first region, andthe writing management unit references the coloring information to writethe write target data of which the access frequency is low estimatedbased on the data characteristic into the second region.
 8. The memorymanagement device according to claim 1, further comprising a readingmanagement unit that determines whether to cache read target data in thevolatile semiconductor memory by referencing the coloring information ofthe read target data when the read target data is read from thenonvolatile semiconductor memory.
 9. The memory management deviceaccording to claim 1, wherein the nonvolatile semiconductor memory is aNAND flash memory and the volatile semiconductor memory is a DRAM. 10.The memory management device according to claim 6, wherein the at leastone of the access frequency, the data life, and the importance estimatedbased on the data characteristic of the write target data is determinedbased on at least one of a characteristic of a file in a file system ofthe write target data and a characteristic of a data type when a programin which the write target data is handled is executed.
 11. The memorymanagement device according to claim 6, wherein the at least one of theaccess frequency, the data life, and the importance estimated based onthe data characteristic of the write target data is determined based onan extension of the write target data.
 12. The memory management deviceaccording to claim 6, wherein the at least one of the access frequency,the data life, and the importance estimated based on the datacharacteristic of the write target data is determined based on anarrangement region of a kernel of the write target data.
 13. The memorymanagement device according to claim 5, wherein an access frequency tothe write target data is calculated based on the access count to thewrite target data and the writing management unit references the accessfrequency to determine a writing region in the nonvolatile semiconductormemory of the write target data.
 14. The memory management deviceaccording to claim 13, further comprising a relocation unit thatrelocates data by referencing the access count or the access frequencyof the data in the nonvolatile semiconductor memory and the volatilesemiconductor memory.
 15. The memory management device according toclaim 6, wherein the nonvolatile semiconductor memory comprises a firstregion and a second region and the second region can store moremulti-bit data than the first region, the writing management unitreferences the coloring information, writes the write target data ofwhich the data life is short estimated based on the data characteristicinto the volatile semiconductor memory, writes the write target data ofwhich the data life is long estimated based on the data characteristicand of which the importance is high estimated based on the datacharacteristic into the first region of the nonvolatile semiconductormemory, and writes the write target data of which the data life is longestimated based on the data characteristic and of which the importanceis low estimated based on the data characteristic into the second regionof the nonvolatile semiconductor memory.
 16. The memory managementdevice according to claim 6, wherein the coloring information furthercomprises an access count to the write target data, the nonvolatilesemiconductor memory comprises a first region and a second region, andthe writing management unit references the access frequency calculatedbased on the access count to the write target data to determine theregion into which the write target data is written from the first regionor the second region.
 17. The memory management device according toclaim 1, wherein the writing management unit determines a writing regionbased on the coloring information and memory usage informationcomprising an erasure count for each predetermined region of thenonvolatile semiconductor memory so that an occurrence count of erasureprocessing for the nonvolatile semiconductor memory by wear leveling issuppressed.
 18. An information processing device, comprising: aprocessor; a nonvolatile semiconductor memory and a volatilesemiconductor memory used as a main memory; and a memory management unitthat controls writing into and reading from the nonvolatilesemiconductor memory and the volatile semiconductor memory in responseto a writing request and a reading request from the processor, whereinthe memory management unit, including: a coloring information storageunit that stores coloring information generated based on a datacharacteristic of write target data to be written into at least one ofthe nonvolatile semiconductor memory and the volatile semiconductormemory; and a writing management unit that references the coloringinformation to determine a region into which the write target data iswritten from the nonvolatile semiconductor memory and the volatilesemiconductor memory.
 19. The information processing device according toclaim 18, wherein the coloring information comprising at least one of anaccess frequency, a data life, and importance estimated based on thedata characteristic of the write target data.
 20. The informationprocessing device according to claim 18, wherein the memory managementunit further comprises a reading management unit that determines whetherto cache read target data in the volatile semiconductor memory byreferencing the coloring information of the read target data when theread target data is read from the nonvolatile semiconductor memory. 21.The information processing device according to claim 18, wherein thecoloring information further comprises an access count to the writetarget data and the access count is counted by a counter included in theprocessor.